From c3a93013bc8f266e128d77b2bccbd244d178ab5b Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Sun, 21 Apr 2013 12:20:19 +0000 Subject: [PATCH] ARM: fix part of test which actually needed an asserts build This should fix a buildbot failure that occurred after r179977. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179978 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../CodeGen/ARM/gpr-paired-spill-thumbinst.ll | 30 +++++++++++++++++++ test/CodeGen/ARM/gpr-paired-spill.ll | 6 ---- 2 files changed, 30 insertions(+), 6 deletions(-) create mode 100644 test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll diff --git a/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll b/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll new file mode 100644 index 00000000000..00027119f9e --- /dev/null +++ b/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll @@ -0,0 +1,30 @@ +; REQUIRES: asserts +; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < %s 2>&1 | FileCheck %s + +; This test makes sure spills of 64-bit pairs in Thumb mode actually +; generate thumb instructions. Previously we were inserting an ARM +; STMIA which happened to have the same encoding. + +define void @foo(i64* %addr) { + %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + + ; Make sure we are actually creating the Thumb versions of the spill + ; instructions. +; CHECK: t2STRDi8 +; CHECK: t2LDRDi8 + + store volatile i64 %val1, i64* %addr + store volatile i64 %val2, i64* %addr + store volatile i64 %val3, i64* %addr + store volatile i64 %val4, i64* %addr + store volatile i64 %val5, i64* %addr + store volatile i64 %val6, i64* %addr + store volatile i64 %val7, i64* %addr + ret void +} diff --git a/test/CodeGen/ARM/gpr-paired-spill.ll b/test/CodeGen/ARM/gpr-paired-spill.ll index 86088326b5b..ef3e5a54a2d 100644 --- a/test/CodeGen/ARM/gpr-paired-spill.ll +++ b/test/CodeGen/ARM/gpr-paired-spill.ll @@ -1,7 +1,6 @@ ; RUN: llc -mtriple=armv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD ; RUN: llc -mtriple=armv4-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITHOUT-LDRD ; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD -; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < %s 2>&1 | FileCheck %s --check-prefix=INSTRS-ARE-THUMB define void @foo(i64* %addr) { %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) @@ -34,11 +33,6 @@ define void @foo(i64* %addr) { ; CHECK-WITHOUT-LDRD: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}} ; CHECK-WITHOUT-LDRD: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}} - ; Make sure we are actually creating the Thumb versions of the spill - ; instructions. -; INSTRS-ARE-THUMB: t2STRDi8 -; INSTRS-ARE-THUMB: t2LDRDi8 - store volatile i64 %val1, i64* %addr store volatile i64 %val2, i64* %addr store volatile i64 %val3, i64* %addr -- 2.34.1