From bd30ce4311e158f1bfc6c95987ffbbad2193fef3 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Fri, 24 Sep 2010 22:41:41 +0000
Subject: [PATCH] More pseudo instruction scheduling itinerary fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrThumb2.td |  2 +-
 lib/Target/ARM/ARMSchedule.td    |  1 +
 lib/Target/ARM/ARMScheduleA8.td  | 10 +++++++++-
 lib/Target/ARM/ARMScheduleA9.td  |  8 +++++++-
 lib/Target/ARM/ARMScheduleV6.td  |  7 +++++++
 5 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 0534097d438..aa12a92d357 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2711,7 +2711,7 @@ def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
 // scheduling.
 let canFoldAsLoad = 1, isReMaterializable = 1 in
 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
-                   NoItinerary,
+                   IIC_iLoadiALU,
                    "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
                [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
                                            imm:$cp))]>,
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index 4b02e945f75..aaad402a447 100644
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -45,6 +45,7 @@ def IIC_iLoadru    : InstrItinClass;
 def IIC_iLoadsiu   : InstrItinClass;
 def IIC_iLoadm     : InstrItinClass<0>;  // micro-coded
 def IIC_iLoadmBr   : InstrItinClass<0>;  // micro-coded
+def IIC_iLoadiALU  : InstrItinClass;
 def IIC_iStorei    : InstrItinClass;
 def IIC_iStorer    : InstrItinClass;
 def IIC_iStoresi   : InstrItinClass;
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td
index 179c121ca03..3cbfe751f53 100644
--- a/lib/Target/ARM/ARMScheduleA8.td
+++ b/lib/Target/ARM/ARMScheduleA8.td
@@ -51,7 +51,7 @@ def CortexA8Itineraries : ProcessorItineraries<
   // Move instructions, unconditional
   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
-                             InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
+                             InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
@@ -133,6 +133,14 @@ def CortexA8Itineraries : ProcessorItineraries<
                                 InstrStage<1, [A8_LdSt0]>,
                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
+                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+                                InstrStage<1, [A8_LdSt0]>,
+                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
+
+
   // Integer store pipeline
   //
   // use A8_Issue to enforce the 1 load/store per cycle limit
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td
index b37b3948f17..a4be5a73746 100644
--- a/lib/Target/ARM/ARMScheduleA9.td
+++ b/lib/Target/ARM/ARMScheduleA9.td
@@ -33,7 +33,7 @@ def CortexA9Itineraries : ProcessorItineraries<
   // Move instructions, unconditional
   InstrItinData<IIC_iMOVi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
   InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
-                               InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
+                               InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
   InstrItinData<IIC_iMOVr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsr  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
@@ -115,6 +115,12 @@ def CortexA9Itineraries : ProcessorItineraries<
                                 InstrStage<1, [A9_LSPipe]>,
                                 InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Pipe1]>,
+                                InstrStage<1, [A9_LSPipe]>,
+                                InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [4, 1]>,
+
   // Integer store pipeline
   ///
   // Immediate offset
diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td
index b382a7a5191..52d2dc1e494 100644
--- a/lib/Target/ARM/ARMScheduleV6.td
+++ b/lib/Target/ARM/ARMScheduleV6.td
@@ -46,6 +46,8 @@ def ARMV6Itineraries : ProcessorItineraries<
   InstrItinData<IIC_iMOVr    , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
   InstrItinData<IIC_iMOVsi   , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
   InstrItinData<IIC_iMOVsr   , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
+  InstrItinData<IIC_iMOVix2  , [InstrStage<1, [V6_Pipe]>,
+                                InstrStage<1, [V6_Pipe]>], [2]>,
   //
   // Move instructions, conditional
   InstrItinData<IIC_iCMOVi   , [InstrStage<1, [V6_Pipe]>], [3]>,
@@ -91,6 +93,11 @@ def ARMV6Itineraries : ProcessorItineraries<
   InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>,
                                 InstrStage<1, [V6_Pipe]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,
+                                InstrStage<1, [V6_Pipe]>], [3, 1]>,
+
   // Integer store pipeline
   //
   // Immediate offset
-- 
2.34.1