From b9bee10b2158253e222eb8dd5f0ae0452740ace3 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Fri, 11 Oct 2013 10:00:06 +0000 Subject: [PATCH] [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrInfo.td | 20 ++-- lib/Target/Mips/MipsSEISelLowering.cpp | 23 +++++ test/CodeGen/Mips/msa/arithmetic_float.ll | 112 ++++++++++++++++++++++ 3 files changed, 143 insertions(+), 12 deletions(-) diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 48c204af92e..4a95bc57046 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1771,15 +1771,11 @@ class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, MSA128DOpnd, MSA128WOpnd>; -class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", int_mips_ffint_s_w, - MSA128WOpnd>; -class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", int_mips_ffint_s_d, - MSA128DOpnd>; +class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; +class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; -class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", int_mips_ffint_u_w, - MSA128WOpnd>; -class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", int_mips_ffint_u_d, - MSA128DOpnd>; +class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; +class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, MSA128WOpnd, MSA128HOpnd>; @@ -1890,14 +1886,14 @@ class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, MSA128DOpnd>; -class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", int_mips_ftrunc_s_w, +class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, MSA128WOpnd>; -class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", int_mips_ftrunc_s_d, +class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, MSA128DOpnd>; -class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", int_mips_ftrunc_u_w, +class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, MSA128WOpnd>; -class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", int_mips_ftrunc_u_d, +class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, MSA128DOpnd>; class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 7fe0f4b4598..a08d157fedf 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -188,6 +188,13 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::VSELECT, Ty, Legal); setOperationAction(ISD::XOR, Ty, Legal); + if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { + setOperationAction(ISD::FP_TO_SINT, Ty, Legal); + setOperationAction(ISD::FP_TO_UINT, Ty, Legal); + setOperationAction(ISD::SINT_TO_FP, Ty, Legal); + setOperationAction(ISD::UINT_TO_FP, Ty, Legal); + } + setOperationAction(ISD::SETCC, Ty, Legal); setCondCodeAction(ISD::SETNE, Ty, Expand); setCondCodeAction(ISD::SETGE, Ty, Expand); @@ -1300,6 +1307,14 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_fdiv_d: return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ffint_u_w: + case Intrinsic::mips_ffint_u_d: + return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), + Op->getOperand(1)); + case Intrinsic::mips_ffint_s_w: + case Intrinsic::mips_ffint_s_d: + return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), + Op->getOperand(1)); case Intrinsic::mips_fill_b: case Intrinsic::mips_fill_h: case Intrinsic::mips_fill_w: @@ -1331,6 +1346,14 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_fsub_d: return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ftrunc_u_w: + case Intrinsic::mips_ftrunc_u_d: + return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), + Op->getOperand(1)); + case Intrinsic::mips_ftrunc_s_w: + case Intrinsic::mips_ftrunc_s_d: + return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), + Op->getOperand(1)); case Intrinsic::mips_ilvev_b: case Intrinsic::mips_ilvev_h: case Intrinsic::mips_ilvev_w: diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll index 0c106f826de..82e05ad8f90 100644 --- a/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -184,6 +184,118 @@ define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind { ; CHECK: .size fsqrt_v2f64 } +define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind { + ; CHECK: ffint_u_v4f32: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = uitofp <4 x i32> %1 to <4 x float> + ; CHECK-DAG: ffint_u.w [[R3:\$w[0-9]+]], [[R1]] + store <4 x float> %2, <4 x float>* %c + ; CHECK-DAG: st.w [[R3]], 0($4) + + ret void + ; CHECK: .size ffint_u_v4f32 +} + +define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind { + ; CHECK: ffint_u_v2f64: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = uitofp <2 x i64> %1 to <2 x double> + ; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R1]] + store <2 x double> %2, <2 x double>* %c + ; CHECK-DAG: st.d [[R3]], 0($4) + + ret void + ; CHECK: .size ffint_u_v2f64 +} + +define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind { + ; CHECK: ffint_s_v4f32: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = sitofp <4 x i32> %1 to <4 x float> + ; CHECK-DAG: ffint_s.w [[R3:\$w[0-9]+]], [[R1]] + store <4 x float> %2, <4 x float>* %c + ; CHECK-DAG: st.w [[R3]], 0($4) + + ret void + ; CHECK: .size ffint_s_v4f32 +} + +define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind { + ; CHECK: ffint_s_v2f64: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = sitofp <2 x i64> %1 to <2 x double> + ; CHECK-DAG: ffint_s.d [[R3:\$w[0-9]+]], [[R1]] + store <2 x double> %2, <2 x double>* %c + ; CHECK-DAG: st.d [[R3]], 0($4) + + ret void + ; CHECK: .size ffint_s_v2f64 +} + +define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind { + ; CHECK: ftrunc_u_v4f32: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = fptoui <4 x float> %1 to <4 x i32> + ; CHECK-DAG: ftrunc_u.w [[R3:\$w[0-9]+]], [[R1]] + store <4 x i32> %2, <4 x i32>* %c + ; CHECK-DAG: st.w [[R3]], 0($4) + + ret void + ; CHECK: .size ftrunc_u_v4f32 +} + +define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind { + ; CHECK: ftrunc_u_v2f64: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = fptoui <2 x double> %1 to <2 x i64> + ; CHECK-DAG: ftrunc_u.d [[R3:\$w[0-9]+]], [[R1]] + store <2 x i64> %2, <2 x i64>* %c + ; CHECK-DAG: st.d [[R3]], 0($4) + + ret void + ; CHECK: .size ftrunc_u_v2f64 +} + +define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind { + ; CHECK: ftrunc_s_v4f32: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = fptosi <4 x float> %1 to <4 x i32> + ; CHECK-DAG: ftrunc_s.w [[R3:\$w[0-9]+]], [[R1]] + store <4 x i32> %2, <4 x i32>* %c + ; CHECK-DAG: st.w [[R3]], 0($4) + + ret void + ; CHECK: .size ftrunc_s_v4f32 +} + +define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind { + ; CHECK: ftrunc_s_v2f64: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = fptosi <2 x double> %1 to <2 x i64> + ; CHECK-DAG: ftrunc_s.d [[R3:\$w[0-9]+]], [[R1]] + store <2 x i64> %2, <2 x i64>* %c + ; CHECK-DAG: st.d [[R3]], 0($4) + + ret void + ; CHECK: .size ftrunc_s_v2f64 +} + declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val) declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val) declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val) -- 2.34.1