From b84ad4aa7dacfba5337520740d47770f2200201c Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 15 Mar 2012 21:34:14 +0000 Subject: [PATCH] ARM case-insensitive checking for APSR_nzcv. rdar://11056591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrVFP.td | 2 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 8 +++++--- lib/Target/ARM/AsmParser/x | 23 +++++++++++++++++++++++ test/CodeGen/ARM/fpcmp-opt.ll | 2 +- test/CodeGen/ARM/fpcmp_ueq.ll | 2 +- test/CodeGen/ARM/ifcvt11.ll | 4 ++-- test/MC/ARM/simple-fp-encoding.s | 6 ++++-- 7 files changed, 37 insertions(+), 10 deletions(-) create mode 100644 lib/Target/ARM/AsmParser/x diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index b29b31ef35e..307e25eefbe 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -1198,7 +1198,7 @@ class MovFromVFP opc19_16, dag oops, dag iops, string opc, string asm, // to APSR. let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), - "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>; + "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; // Application level FPSCR -> GPR let hasSideEffects = 1, Uses = [FPSCR] in diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index af973e8c1f8..29a9b0d844a 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3258,7 +3258,8 @@ parseMSRMaskOperand(SmallVectorImpl &Operands) { if (isMClass()) { // See ARMv6-M 10.1.1 - unsigned FlagsVal = StringSwitch(Mask) + std::string Name = Mask.lower(); + unsigned FlagsVal = StringSwitch(Name) .Case("apsr", 0) .Case("iapsr", 1) .Case("eapsr", 2) @@ -4432,10 +4433,11 @@ bool ARMAsmParser::parseOperand(SmallVectorImpl &Operands, else if (Res == -1) // irrecoverable error return true; // If this is VMRS, check for the apsr_nzcv operand. - if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { + if (Mnemonic == "vmrs" && + Parser.getTok().getString().equals_lower("apsr_nzcv")) { S = Parser.getTok().getLoc(); Parser.Lex(); - Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S)); + Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); return false; } diff --git a/lib/Target/ARM/AsmParser/x b/lib/Target/ARM/AsmParser/x new file mode 100644 index 00000000000..1496e70647d --- /dev/null +++ b/lib/Target/ARM/AsmParser/x @@ -0,0 +1,23 @@ +diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +index af973e8..cbdae2a 100644 +--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp ++++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +@@ -3254,7 +3254,8 @@ parseMSRMaskOperand(SmallVectorImpl &Operands) { + SMLoc S = Parser.getTok().getLoc(); + const AsmToken &Tok = Parser.getTok(); + assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); +- StringRef Mask = Tok.getString(); ++ std::string MaskStr = Tok.getString().lower(); ++ StringRef Mask = MaskStr; // convenience for slice() and such. + + if (isMClass()) { + // See ARMv6-M 10.1.1 +@@ -3290,7 +3291,7 @@ parseMSRMaskOperand(SmallVectorImpl &Operands) { + // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" + size_t Start = 0, Next = Mask.find('_'); + StringRef Flags = ""; +- std::string SpecReg = Mask.slice(Start, Next).lower(); ++ StringRef SpecReg = Mask.slice(Start, Next); + if (Next != StringRef::npos) + Flags = Mask.slice(Next+1, Mask.size()); + diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll index 80925c7de73..2d8f7108e0e 100644 --- a/test/CodeGen/ARM/fpcmp-opt.ll +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -9,7 +9,7 @@ entry: ; CHECK: vldr [[S0:s[0-9]+]], ; CHECK: vldr [[S1:s[0-9]+]], ; CHECK: vcmpe.f32 [[S1]], [[S0]] -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: beq %0 = load float* %a %1 = load float* %b diff --git a/test/CodeGen/ARM/fpcmp_ueq.ll b/test/CodeGen/ARM/fpcmp_ueq.ll index 2e6b3e3167a..4a4c5b1c8b0 100644 --- a/test/CodeGen/ARM/fpcmp_ueq.ll +++ b/test/CodeGen/ARM/fpcmp_ueq.ll @@ -5,7 +5,7 @@ define i32 @f7(float %a, float %b) { entry: ; CHECK: f7: ; CHECK: vcmpe.f32 -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: movweq ; CHECK-NOT: vmrs ; CHECK: movwvs diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll index 63f8557d555..0f142eef7a3 100644 --- a/test/CodeGen/ARM/ifcvt11.ll +++ b/test/CodeGen/ARM/ifcvt11.ll @@ -18,7 +18,7 @@ bb.nph: ; preds = %entry bb: ; preds = %bb4, %bb.nph ; CHECK: vcmpe.f64 -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr %r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ] %n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ] %scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0 @@ -33,7 +33,7 @@ bb1: ; preds = %bb ; CHECK-NOT: vcmpemi ; CHECK-NOT: vmrsmi ; CHECK: vcmpe.f64 -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr %scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2 %6 = load double* %scevgep12, align 4 %7 = fcmp uge double %3, %6 diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index de8f3a70a9d..d6a9ccca915 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -120,8 +120,10 @@ @ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] vnmls.f32 s1, s2, s0 -@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] -@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] + vmrs APSR_nzcv, fpscr vmrs apsr_nzcv, fpscr fmstat -- 2.34.1