From b66e943d4cfa4a48ad028898d232754ecd3202c1 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 1 Apr 2012 21:20:14 +0000 Subject: [PATCH] Fix some 80-col. violations I introduced with the A2 PPC64 core. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPC.td | 3 +- lib/Target/PowerPC/PPCScheduleA2.td | 186 ++++++++++++++++++---------- 2 files changed, 126 insertions(+), 63 deletions(-) diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index ca0aa331ca3..c554d39434c 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -90,7 +90,8 @@ def : Processor<"g5", G5Itineraries, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE, FeatureFSqrt, FeatureSTFIWX, - Feature64Bit /*, Feature64BitRegs */]>; + Feature64Bit + /*, Feature64BitRegs */]>; def : Processor<"ppc", G3Itineraries, [Directive32]>; def : Processor<"ppc64", G5Itineraries, [Directive64, FeatureAltivec, diff --git a/lib/Target/PowerPC/PPCScheduleA2.td b/lib/Target/PowerPC/PPCScheduleA2.td index 2c728fe4645..857ba40ff62 100644 --- a/lib/Target/PowerPC/PPCScheduleA2.td +++ b/lib/Target/PowerPC/PPCScheduleA2.td @@ -60,7 +60,8 @@ def PPCA2Itineraries : ProcessorItineraries< IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6, FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6], [CR_Bypass, GPR_Bypass, FPR_Bypass], [ - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -70,7 +71,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -80,7 +82,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [CR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -90,7 +93,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>], [53, 7, 7], [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -100,7 +104,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -110,7 +115,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -120,7 +126,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -130,7 +137,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -140,7 +148,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -150,7 +159,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -160,7 +170,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -170,7 +181,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -180,7 +192,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -190,7 +203,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [CR_Bypass, CR_Bypass, CR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -200,7 +214,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [CR_Bypass, CR_Bypass, CR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -210,7 +225,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7, 7], [CR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -220,7 +236,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [13, 11], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -230,7 +247,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [13, 11], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -240,7 +258,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [13, 11], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -250,7 +269,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7], [GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -260,7 +280,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [13, 7], [GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -270,7 +291,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -280,7 +302,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7, 7], [NoBypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -290,7 +313,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7, 7], [FPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -300,7 +324,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7, 7], [FPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -310,7 +335,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -320,7 +346,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [14, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, @@ -330,7 +357,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [26, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -340,7 +368,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [13, 7], [GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, @@ -350,7 +379,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [26, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -360,7 +390,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [13, 7], [GPR_Bypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, @@ -370,7 +401,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [26, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, @@ -380,7 +412,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [26, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -388,7 +421,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>, InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -396,7 +430,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -406,7 +441,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7], [GPR_Bypass, NoBypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -416,7 +452,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -426,7 +463,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -434,7 +472,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -444,7 +483,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [10, 7], [GPR_Bypass, CR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -454,7 +494,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7], [GPR_Bypass, NoBypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -464,7 +505,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -474,7 +516,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], [29, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -484,7 +527,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], [15, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -494,7 +538,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], [29, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -504,7 +549,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], [29, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -514,7 +560,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], [29, 7], [NoBypass, GPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -524,7 +571,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], [15, 7, 7], [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -534,40 +582,53 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], [13, 7, 7], [CR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>, - InstrStage<71, [FEX1], 0>, InstrStage<71, [FEX2], 0>, - InstrStage<71, [FEX3], 0>, InstrStage<71, [FEX4], 0>, - InstrStage<71, [FEX5], 0>, InstrStage<71, [FEX6]>], + InstrStage<71, [FEX1], 0>, + InstrStage<71, [FEX2], 0>, + InstrStage<71, [FEX3], 0>, + InstrStage<71, [FEX4], 0>, + InstrStage<71, [FEX5], 0>, + InstrStage<71, [FEX6]>], [86, 7, 7], [NoBypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>, - InstrStage<58, [FEX1], 0>, InstrStage<58, [FEX2], 0>, - InstrStage<58, [FEX3], 0>, InstrStage<58, [FEX4], 0>, - InstrStage<58, [FEX5], 0>, InstrStage<58, [FEX6]>], + InstrStage<58, [FEX1], 0>, + InstrStage<58, [FEX2], 0>, + InstrStage<58, [FEX3], 0>, + InstrStage<58, [FEX4], 0>, + InstrStage<58, [FEX5], 0>, + InstrStage<58, [FEX6]>], [73, 7, 7], [NoBypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>, - InstrStage<68, [FEX1], 0>, InstrStage<68, [FEX2], 0>, - InstrStage<68, [FEX3], 0>, InstrStage<68, [FEX4], 0>, - InstrStage<68, [FEX5], 0>, InstrStage<68, [FEX6]>], + InstrStage<68, [FEX1], 0>, + InstrStage<68, [FEX2], 0>, + InstrStage<68, [FEX3], 0>, + InstrStage<68, [FEX4], 0>, + InstrStage<68, [FEX5], 0>, + InstrStage<68, [FEX6]>], [86, 7], // FIXME: should be [86, 7] for double // and [82, 7] for single. Likewise, // the FEX? cycle count should be 68 // for double and 64 for single. [NoBypass, FPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, @@ -577,7 +638,8 @@ def PPCA2Itineraries : ProcessorItineraries< InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], [15, 7, 7, 7], [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData, + InstrItinData, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7]>, InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, -- 2.34.1