From b5f011715c96acb715f50c22dec467511c61db25 Mon Sep 17 00:00:00 2001 From: Vasileios Kalintiris Date: Wed, 7 Oct 2015 18:14:24 +0000 Subject: [PATCH] [mips][FastISel] Simple refactoring of MipsFastISel::emitLogicalOP(). NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249580 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsFastISel.cpp | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 7fdfeefb31f..da7b1735985 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -236,32 +236,36 @@ unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, std::swap(LHS, RHS); unsigned Opc; - if (ISDOpc == ISD::AND) { - Opc = Mips::AND; - } else if (ISDOpc == ISD::OR) { - Opc = Mips::OR; - } else if (ISDOpc == ISD::XOR) { - Opc = Mips::XOR; - } else + switch (ISDOpc) { + case ISD::AND: + Opc = Mips::AND; + break; + case ISD::OR: + Opc = Mips::OR; + break; + case ISD::XOR: + Opc = Mips::XOR; + break; + default: llvm_unreachable("unexpected opcode"); + } unsigned LHSReg = getRegForValue(LHS); - unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); - if (!ResultReg) - return 0; - - unsigned RHSReg; if (!LHSReg) return 0; + unsigned RHSReg; if (const auto *C = dyn_cast(RHS)) RHSReg = materializeInt(C, MVT::i32); else RHSReg = getRegForValue(RHS); - if (!RHSReg) return 0; + unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); + if (!ResultReg) + return 0; + emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); return ResultReg; } -- 2.34.1