From b3727fe3ec3b3a718935a6d6c6561e9a58a14546 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Fri, 28 Oct 2011 20:43:24 +0000 Subject: [PATCH] Specify that the high bit of the alignment field is fixed to 0 on these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143220 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrNEON.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 75418aa9758..3023a3419dd 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -389,7 +389,7 @@ multiclass VLD1D3WB op7_4, string Dt> { "vld1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. - let Inst{5-4} = Rn{5-4}; + let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDInstruction"; let AsmMatchConverter = "cvtVLDwbFixed"; } @@ -397,7 +397,7 @@ multiclass VLD1D3WB op7_4, string Dt> { (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, "vld1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDInstruction"; let AsmMatchConverter = "cvtVLDwbRegister"; } -- 2.34.1