From b2e79a8e69d672c367a8a3fcb9138f80d7e3e7e0 Mon Sep 17 00:00:00 2001 From: Jozef Kolek Date: Fri, 20 Feb 2015 20:26:52 +0000 Subject: [PATCH 1/1] Reversed revision 229706. The reason is regression, which is caused by the usage of instruction ADDU16 by CodeGen. For this instruction an improper register is allocated, i.e. the register that is not from register set defined for the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230053 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrInfo.td | 6 ++---- lib/Target/Mips/MipsInstrInfo.td | 3 +-- test/CodeGen/Mips/micromips-addu16.ll | 18 ------------------ test/CodeGen/Mips/micromips-subu16.ll | 18 ------------------ 4 files changed, 3 insertions(+), 42 deletions(-) delete mode 100644 test/CodeGen/Mips/micromips-addu16.ll delete mode 100644 test/CodeGen/Mips/micromips-subu16.ll diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 19120202af7..e20df2f4e62 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -642,10 +642,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { LW_FM_MM<0xc>; /// Arithmetic Instructions (3-Operand, R-Type) - def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, - ADD_FM_MM<0, 0x150>; - def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, - ADD_FM_MM<0, 0x1d0>; + def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>; + def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>; def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>; def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>; def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index c33b349a955..f2fdff8ff7c 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1140,13 +1140,12 @@ def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, ADDI_FM<0xe>; def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; -let AdditionalPredicates = [NotInMicroMips] in { + /// Arithmetic Instructions (3-Operand, R-Type) def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, ADD_FM<0, 0x21>; def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, ADD_FM<0, 0x23>; -} let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; diff --git a/test/CodeGen/Mips/micromips-addu16.ll b/test/CodeGen/Mips/micromips-addu16.ll deleted file mode 100644 index adebaf03bcf..00000000000 --- a/test/CodeGen/Mips/micromips-addu16.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ -; RUN: -relocation-model=pic -O3 < %s | FileCheck %s - -define i32 @main() { -entry: - %retval = alloca i32, align 4 - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32* %b, align 4 - %1 = load i32* %c, align 4 - %add = add nsw i32 %0, %1 - store i32 %add, i32* %a, align 4 - ret i32 0 -} - -; CHECK: addu16 diff --git a/test/CodeGen/Mips/micromips-subu16.ll b/test/CodeGen/Mips/micromips-subu16.ll deleted file mode 100644 index 4ca16ef7c61..00000000000 --- a/test/CodeGen/Mips/micromips-subu16.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ -; RUN: -relocation-model=pic -O3 < %s | FileCheck %s - -define i32 @main() { -entry: - %retval = alloca i32, align 4 - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32* %b, align 4 - %1 = load i32* %c, align 4 - %sub = sub nsw i32 %0, %1 - store i32 %sub, i32* %a, align 4 - ret i32 0 -} - -; CHECK: subu16 -- 2.34.1