From ab48d10effb223de0c9516ccae616a80fef27df8 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Sat, 14 Sep 2013 07:15:21 +0000 Subject: [PATCH] Support for microMIPS DIV instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrInfo.td | 4 ++++ lib/Target/Mips/MipsInstrInfo.td | 2 +- test/MC/Disassembler/Mips/micromips.txt | 6 ++++++ test/MC/Disassembler/Mips/micromips_le.txt | 6 ++++++ test/MC/Mips/micromips-alu-instructions.s | 6 ++++++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index b274d6fa000..ee43299b560 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -69,6 +69,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { MULT_FM_MM<0x22c>; def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>, MULT_FM_MM<0x26c>; + def SDIV_MM : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, + MULT_FM_MM<0x2ac>; + def UDIV_MM : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, + MULT_FM_MM<0x2ec>; /// Shift Instructions def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd>, diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index e4b51ceeeeb..1c6b3cd9063 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -681,7 +681,7 @@ class MAddSubPseudo class Div DefRegs> : InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), - [], itin, FrmR> { + [], itin, FrmR, opstr> { let Defs = DefRegs; } diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt index b963b05a5e0..a6a3575a5aa 100644 --- a/test/MC/Disassembler/Mips/micromips.txt +++ b/test/MC/Disassembler/Mips/micromips.txt @@ -88,6 +88,12 @@ # CHECK: multu $9, $7 0x00 0xe9 0x9b 0x3c +# CHECK-EB: div $zero, $9, $7 +0x00 0xe9 0xab 0x3c + +# CHECK-EB: divu $zero, $9, $7 +0x00 0xe9 0xbb 0x3c + # CHECK: sll $4, $3, 7 0x00 0x83 0x38 0x00 diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt index ef08158d35d..253223cc458 100644 --- a/test/MC/Disassembler/Mips/micromips_le.txt +++ b/test/MC/Disassembler/Mips/micromips_le.txt @@ -88,6 +88,12 @@ # CHECK: multu $9, $7 0xe9 0x00 0x3c 0x9b +# CHECK: div $zero, $9, $7 +0xe9 0x00 0x3c 0xab + +# CHECK: divu $zero, $9, $7 +0xe9 0x00 0x3c 0xbb + # CHECK: sll $4, $3, 7 0x83 0x00 0x00 0x38 diff --git a/test/MC/Mips/micromips-alu-instructions.s b/test/MC/Mips/micromips-alu-instructions.s index 3f6079cf673..bd5cdd3ba86 100644 --- a/test/MC/Mips/micromips-alu-instructions.s +++ b/test/MC/Mips/micromips-alu-instructions.s @@ -36,6 +36,8 @@ # CHECK-EL: mul $9, $6, $7 # encoding: [0xe6,0x00,0x10,0x4a] # CHECK-EL: mult $9, $7 # encoding: [0xe9,0x00,0x3c,0x8b] # CHECK-EL: multu $9, $7 # encoding: [0xe9,0x00,0x3c,0x9b] +# CHECK-EL: div $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xab] +# CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -68,6 +70,8 @@ # CHECK-EB: mul $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x10] # CHECK-EB: mult $9, $7 # encoding: [0x00,0xe9,0x8b,0x3c] # CHECK-EB: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c] +# CHECK-EB: div $zero, $9, $7 # encoding: [0x00,0xe9,0xab,0x3c] +# CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c] add $9, $6, $7 add $9, $6, 17767 addu $9, $6, -15001 @@ -97,3 +101,5 @@ mul $9, $6, $7 mult $9, $7 multu $9, $7 + div $0, $9, $7 + divu $0, $9, $7 -- 2.34.1