From a7250ddc2848bc15f96abd15a4dd872abdc2d08b Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 16 Oct 2008 00:03:00 +0000 Subject: [PATCH] Fix the predicate for memop64 to be a regular load, not just an unindexed load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57612 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrSSE.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 1ae9935473b..0a5089d1ab1 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -134,7 +134,7 @@ def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; // SSSE3 uses MMX registers for some instructions. They aren't aligned on a // 16-byte boundary. // FIXME: 8 byte alignment for mmx reads is not required -def memop64 : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ +def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ return cast(N)->getAlignment() >= 8; }]>; -- 2.34.1