From a66aacf6d7e57b21dcd9e866d28749567cfba74b Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 2 Jul 2013 00:00:02 +0000 Subject: [PATCH] [mips] Add new InstrItinClasses for move from/to coprocessor instructions and floating point loads and stores. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 22 +++++------ lib/Target/Mips/MipsInstrFPU.td | 62 +++++++++++++++--------------- lib/Target/Mips/MipsInstrInfo.td | 34 +++++++++------- lib/Target/Mips/MipsSchedule.td | 8 +++- 4 files changed, 70 insertions(+), 56 deletions(-) diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index df717fe2d2e..b55679eea28 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -131,17 +131,17 @@ let Predicates = [HasMips64r2, HasStdEnc], let DecoderNamespace = "Mips64" in { /// Load and Store Instructions /// aligned -defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>; -defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>; -defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>; -defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>; -defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>; -defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>; -defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>; -defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>; -defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>; -defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>; -defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>; +defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8, IILoad>, LW_FM<0x20>; +defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8, IILoad>, LW_FM<0x24>; +defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16, IILoad>, LW_FM<0x21>; +defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16, IILoad>, LW_FM<0x25>; +defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32, IILoad>, LW_FM<0x23>; +defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32, IILoad>, LW_FM<0x27>; +defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8, IIStore>, LW_FM<0x28>; +defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16, IIStore>, LW_FM<0x29>; +defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32, IIStore>, LW_FM<0x2b>; +defm LD : LoadM<"ld", CPU64Regs, load, IILoad>, LW_FM<0x37>; +defm SD : StoreM<"sd", CPU64Regs, store, IIStore>, LW_FM<0x3f>; /// load/store left/right defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 6b2b85963a3..c2acec1d6fe 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -289,10 +289,12 @@ defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; /// Move Control Registers From/To CPU Registers def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>; def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>; -def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>; -def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>; -def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>; -def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>; +def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmoveC1, bitconvert>, MFC1_FM<0>; +def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmoveC1, bitconvert>, MFC1_FM<4>; +def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmoveC1, bitconvert>, + MFC1_FM<1>; +def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmoveC1, bitconvert>, + MFC1_FM<5>; def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>; def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>, @@ -304,86 +306,86 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>, /// Floating Point Memory Instructions let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { - def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem64, load>, LW_FM<0x31>; - def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem64, store>, + def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem64, load>, LW_FM<0x31>; + def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem64, store>, LW_FM<0x39>; - def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem64, load>, + def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem64, load>, LW_FM<0x35> { let isCodeGenOnly =1; } - def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem64, store>, + def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem64, store>, LW_FM<0x3d> { let isCodeGenOnly =1; } } let Predicates = [NotN64, HasStdEnc] in { - def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem, load>, LW_FM<0x31>; - def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem, store>, LW_FM<0x39>; + def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem, load>, LW_FM<0x31>; + def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem, store>, LW_FM<0x39>; } let Predicates = [NotN64, HasMips64, HasStdEnc], DecoderNamespace = "Mips64" in { - def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem, load>, LW_FM<0x35>; - def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem, store>, LW_FM<0x3d>; + def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem, load>, LW_FM<0x35>; + def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem, store>, LW_FM<0x3d>; } let Predicates = [NotN64, NotMips64, HasStdEnc] in { let isPseudo = 1, isCodeGenOnly = 1 in { - def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IILoad, mem, load>; - def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIStore, mem, store>; + def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IIFLoad, mem, load>; + def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIFStore, mem, store>; } - def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IILoad, mem>, LW_FM<0x35>; - def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIStore, mem>, LW_FM<0x3d>; + def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IIFLoad, mem>, LW_FM<0x35>; + def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIFStore, mem>, LW_FM<0x3d>; } // Indexed loads and stores. let Predicates = [HasFPIdx, HasStdEnc] in { - def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IILoad, load>, + def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IIFLoad, load>, LWXC1_FM<0>; - def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIStore, store>, + def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIFStore, store>, SWXC1_FM<8>; } let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in { - def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad, load>, + def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>, LWXC1_FM<1>; - def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore, store>, + def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore, store>, SWXC1_FM<9>; } let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in { - def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad, load>, + def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>, LWXC1_FM<1>; - def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore, store>, + def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore, store>, SWXC1_FM<9>; } // n64 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in { - def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IILoad, load>, + def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFLoad, load>, LWXC1_FM<0>; - def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IILoad, + def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFLoad, load>, LWXC1_FM<1>; - def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIStore, + def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFStore, store>, SWXC1_FM<8>; - def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIStore, + def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFStore, store>, SWXC1_FM<9>; } // Load/store doubleword indexed unaligned. let Predicates = [NotMips64, HasStdEnc] in { - def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad>, + def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad>, LWXC1_FM<0x5>; - def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore>, + def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore>, SWXC1_FM<0xd>; } let Predicates = [HasMips64, HasStdEnc], DecoderNamespace="Mips64" in { - def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad>, + def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad>, LWXC1_FM<0x5>; - def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore>, + def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore>, SWXC1_FM<0xd>; } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 9279bd44265..d2164f72636 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -443,7 +443,8 @@ class FMem op, dag outs, dag ins, string asmstr, list pattern, // Memory Load/Store class Load : + InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr, + string ofsuffix> : InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, !strconcat(opstr, ofsuffix)> { @@ -453,7 +454,8 @@ class Load : + InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr, + string ofsuffix> : InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI, !strconcat(opstr, ofsuffix)> { @@ -463,10 +465,11 @@ class Store { - def NAME : Load, + def NAME : Load, Requires<[NotN64, HasStdEnc]>; - def _P8 : Load, + def _P8 : Load, Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; @@ -475,10 +478,11 @@ multiclass LoadM { - def NAME : Store, + def NAME : Store, Requires<[NotN64, HasStdEnc]>; - def _P8 : Store, + def _P8 : Store, Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; @@ -917,14 +921,16 @@ let Predicates = [HasMips32r2, HasStdEnc] in { /// Load and Store Instructions /// aligned -defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>; -defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>; -defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>; -defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>; -defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>; -defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>; -defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>; -defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>; +defm LB : LoadM<"lb", CPURegs, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; +defm LBu : LoadM<"lbu", CPURegs, zextloadi8, IILoad, addrDefault>, MMRel, + LW_FM<0x24>; +defm LH : LoadM<"lh", CPURegs, sextloadi16, IILoad, addrDefault>, MMRel, + LW_FM<0x21>; +defm LHu : LoadM<"lhu", CPURegs, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; +defm LW : LoadM<"lw", CPURegs, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>; +defm SB : StoreM<"sb", CPURegs, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; +defm SH : StoreM<"sh", CPURegs, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; +defm SW : StoreM<"sw", CPURegs, store, IIStore>, MMRel, LW_FM<0x2b>; /// load/store left/right defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index 1add02ff83e..bf6319dae83 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -35,6 +35,9 @@ def IIFdivDouble : InstrItinClass; def IIFsqrtSingle : InstrItinClass; def IIFsqrtDouble : InstrItinClass; def IIFrecipFsqrtStep : InstrItinClass; +def IIFLoad : InstrItinClass; +def IIFStore : InstrItinClass; +def IIFmoveC1 : InstrItinClass; def IIPseudo : InstrItinClass; //===----------------------------------------------------------------------===// @@ -59,5 +62,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, - InstrItinData]> + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]> ]>; -- 2.34.1