From 9ec5a8f5fd47cca32e6d136fca57e10926dfedfa Mon Sep 17 00:00:00 2001 From: Tang Yun ping Date: Wed, 9 Sep 2015 15:41:47 +0800 Subject: [PATCH] rk312x ddr: fix get bandwidth error 1.Using 64bit width variable to cached the read and write data bandwidth because it may overflow when calculating read and write data bandwidth. 2.Get ddr burst length to calculating bandwidth because lpddr2's burst length may be bl4 or bl8. Change-Id: I28db1793e411fc3e18edc3b6421ab3d397d92aa5 Signed-off-by: Tang Yun ping --- arch/arm/mach-rockchip/ddr_rk3126.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) mode change 100755 => 100644 arch/arm/mach-rockchip/ddr_rk3126.c diff --git a/arch/arm/mach-rockchip/ddr_rk3126.c b/arch/arm/mach-rockchip/ddr_rk3126.c old mode 100755 new mode 100644 index 4f8904b0ad8f..952e2a826719 --- a/arch/arm/mach-rockchip/ddr_rk3126.c +++ b/arch/arm/mach-rockchip/ddr_rk3126.c @@ -2611,6 +2611,12 @@ static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0, struct ddr_bw_inf u64 temp64; uint32 i; uint32 ddr_bw; + uint32 bl; + + if (p_ddr_reg->mem_type == DDR3) + bl = 8; + else + bl = ((pDDR_Reg->MCFG >> 20) & 0x3) << 2; ddr_bw = READ_BW_INFO(); ddr_dfi_monitor_stop(); @@ -2621,15 +2627,20 @@ static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0, struct ddr_bw_inf goto end; ddr_freq = pDDR_Reg->TOGCNT1U; - temp64 = ((u64)ddr_bw_val[ddrbw_wr_num] + (u64)ddr_bw_val[ddrbw_rd_num])*4*100; + temp64 = ((u64)ddr_bw_val[ddrbw_wr_num] + (u64)ddr_bw_val[ddrbw_rd_num]) + * bl / 2 * 100; do_div(temp64, ddr_bw_val[ddrbw_time_num]); ddr_bw_ch0->ddr_percent = (uint32)temp64; - ddr_bw_ch0->ddr_time = ddr_bw_val[ddrbw_time_num]/(ddr_freq*1000); /*ms*/ - ddr_bw_ch0->ddr_wr = (ddr_bw_val[ddrbw_wr_num]*8*ddr_bw*2)*ddr_freq/ddr_bw_val[ddrbw_time_num];/*Byte/us,MB/s*/ - ddr_bw_ch0->ddr_rd = (ddr_bw_val[ddrbw_rd_num]*8*ddr_bw*2)*ddr_freq/ddr_bw_val[ddrbw_time_num]; + ddr_bw_ch0->ddr_time = ddr_bw_val[ddrbw_time_num] / (ddr_freq * 1000); + temp64 = ((u64)ddr_bw_val[ddrbw_wr_num] * bl * ddr_bw * 2) * ddr_freq; + do_div(temp64, ddr_bw_val[ddrbw_time_num]); + ddr_bw_ch0->ddr_wr = (uint32)temp64; + temp64 = ((u64)ddr_bw_val[ddrbw_rd_num] * bl * ddr_bw * 2) * ddr_freq; + do_div(temp64, ddr_bw_val[ddrbw_time_num]); + ddr_bw_ch0->ddr_rd = (uint32)temp64; ddr_bw_ch0->ddr_act = ddr_bw_val[ddrbw_act_num]; - ddr_bw_ch0->ddr_total = ddr_freq*2*ddr_bw*2; + ddr_bw_ch0->ddr_total = ddr_freq * 2 * ddr_bw * 2; end: ddr_dfi_monitor_strat(); } -- 2.34.1