From 9daba6f571437eb90a0fdf477f33cf0cfef9c58b Mon Sep 17 00:00:00 2001 From: James Molloy Date: Mon, 17 Aug 2015 19:37:12 +0000 Subject: [PATCH] [ARM] Fix crash when targetting CPU without NEON We emulate a scalar vmin/vmax with NEON instructions as they don't exist in the VFP ISA. So only mark these as legal when NEON is available. Found here: https://code.google.com/p/chromium/issues/detail?id=521671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245231 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 6 +++--- test/CodeGen/ARM/neon_minmax.ll | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 5bc78c73cfe..fe8da7ffc80 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -950,11 +950,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, } } - if (Subtarget->hasVFP3()) { + if (Subtarget->hasNEON()) { + // vmin and vmax aren't available in a scalar form, so we use + // a NEON instruction with an undef lane instead. setOperationAction(ISD::FMINNAN, MVT::f32, Legal); setOperationAction(ISD::FMAXNAN, MVT::f32, Legal); - } - if (Subtarget->hasNEON()) { setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal); setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal); setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal); diff --git a/test/CodeGen/ARM/neon_minmax.ll b/test/CodeGen/ARM/neon_minmax.ll index 84e4b303c16..883522a829a 100644 --- a/test/CodeGen/ARM/neon_minmax.ll +++ b/test/CodeGen/ARM/neon_minmax.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=-neon %s -o - define float @fmin_ole(float %x) nounwind { ;CHECK-LABEL: fmin_ole: -- 2.34.1