From 9c0a115fbed09bd85f07e6459b77a155d4d46813 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Mon, 22 Dec 2014 21:40:43 +0000 Subject: [PATCH] [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224735 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 4 ++-- lib/Target/Hexagon/HexagonInstrInfo.cpp | 13 ++++------- lib/Target/Hexagon/HexagonInstrInfo.td | 27 ++++++++-------------- lib/Target/Hexagon/HexagonRegisterInfo.cpp | 2 +- test/CodeGen/Hexagon/cext-check.ll | 4 ++-- test/MC/Disassembler/Hexagon/ld.txt | 12 ++++++++++ 6 files changed, 32 insertions(+), 30 deletions(-) diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 18485309058..d8045ffd522 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -407,7 +407,7 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) { if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed; else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed; else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed; - else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed; + else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io; else llvm_unreachable("unknown memory type"); // Build indexed load. @@ -612,7 +612,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) { if (TII->isValidAutoIncImm(LoadedVT, Val)) Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib; else - Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::LDrib; + Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io; } else llvm_unreachable("unknown memory type"); diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index d78315924a5..e2190c30540 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -81,7 +81,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, case Hexagon::LDriw: case Hexagon::LDrid: case Hexagon::LDrih: - case Hexagon::LDrib: + case Hexagon::L2_loadrb_io: case Hexagon::L2_loadrub_io: if (MI->getOperand(2).isFI() && MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { @@ -684,9 +684,8 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::LDriuh_indexed: return isShiftedUInt<6,1>(MI->getOperand(2).getImm()); - case Hexagon::LDrib: + case Hexagon::L2_loadrb_io: case Hexagon::L2_loadrub_io: - case Hexagon::LDrib_indexed: return isUInt<6>(MI->getOperand(2).getImm()); case Hexagon::POST_LDrid: @@ -1130,7 +1129,7 @@ isValidOffset(const int Opcode, const int Offset) const { return (Offset >= Hexagon_MEMH_OFFSET_MIN) && (Offset <= Hexagon_MEMH_OFFSET_MAX); - case Hexagon::LDrib: + case Hexagon::L2_loadrb_io: case Hexagon::STrib: case Hexagon::L2_loadrub_io: return (Offset >= Hexagon_MEMB_OFFSET_MIN) && @@ -1363,10 +1362,8 @@ isConditionalLoad (const MachineInstr* MI) const { case Hexagon::LDrih_cNotPt : case Hexagon::LDrih_indexed_cPt : case Hexagon::LDrih_indexed_cNotPt : - case Hexagon::LDrib_cPt : - case Hexagon::LDrib_cNotPt : - case Hexagon::LDrib_indexed_cPt : - case Hexagon::LDrib_indexed_cNotPt : + case Hexagon::L2_ploadrbt_io: + case Hexagon::L2_ploadrbf_io: case Hexagon::LDriuh_cPt : case Hexagon::LDriuh_cNotPt : case Hexagon::LDriuh_indexed_cPt : diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 58064c3a079..e2a47b135a6 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -1543,6 +1543,7 @@ multiclass LD_Idxd; defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>; } @@ -1586,10 +1587,6 @@ multiclass LD_MEMri, AddrModeRel; - } - let accessSize = HalfWordAccess in { defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel; defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel; @@ -1603,7 +1600,7 @@ let addrMode = BaseImmOffset, isMEMri = "true" in { } def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)), - (LDrib ADDRriS11_0:$addr) >; + (L2_loadrb_io AddrFI:$addr, 0) >; def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)), (L2_loadrub_io AddrFI:$addr, 0) >; @@ -1662,10 +1659,6 @@ multiclass LD_Idxd2, AddrModeRel; - } let accessSize = HalfWordAccess in { defm LDrih_indexed: LD_Idxd2 <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 12, 7>, AddrModeRel; @@ -1683,7 +1676,7 @@ let addrMode = BaseImmOffset in { let AddedComplexity = 20 in { def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))), - (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >; + (L2_loadrb_io IntRegs:$src1, s11_0ExtPred:$offset) >; def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))), (L2_loadrub_io IntRegs:$src1, s11_0ExtPred:$offset) >; @@ -1760,16 +1753,16 @@ let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in { } def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)), - (i32 (LDrib ADDRriS11_0:$addr)) >; + (i32 (L2_loadrb_io AddrFI:$addr, 0)) >; // Load byte any-extend. def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)), - (i32 (LDrib ADDRriS11_0:$addr)) >; + (i32 (L2_loadrb_io AddrFI:$addr, 0)) >; // Indexed load byte any-extend. let AddedComplexity = 20 in def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))), - (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >; + (i32 (L2_loadrb_io IntRegs:$src1, s11_0ImmPred:$offset)) >; def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)), (i32 (LDrih ADDRriS11_1:$addr))>; @@ -3773,7 +3766,7 @@ def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))), // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned. let AddedComplexity = 10 in def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)), - (i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (A2_tfrsi 0x1)))>; + (i32 (A2_and (i32 (L2_loadrb_io AddrFI:$addr, 0)), (A2_tfrsi 0x1)))>; // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo). def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)), @@ -3856,7 +3849,7 @@ def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs. def : Pat<(i1 (load ADDRriS11_2:$addr)), - (i1 (C2_tfrrp (i32 (LDrib ADDRriS11_2:$addr))))>; + (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>; // Map for truncating from 64 immediates to 32 bit immediates. def : Pat<(i32 (trunc (i64 DoubleRegs:$src))), @@ -4026,12 +4019,12 @@ def : Pat <(i64 (sext (i1 PredRegs:$src1))), // Convert sign-extended load back to load and sign extend. // i8 -> i64 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)), - (i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>; + (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>; // Convert any-extended load back to load and sign extend. // i8 -> i64 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)), - (i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>; + (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>; // Convert sign-extended load back to load and sign extend. // i16 -> i64 diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 894da8f1fc1..ddd1d7a1879 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -163,7 +163,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, (MI.getOpcode() == Hexagon::LDrid) || (MI.getOpcode() == Hexagon::LDrih) || (MI.getOpcode() == Hexagon::LDriuh) || - (MI.getOpcode() == Hexagon::LDrib) || + (MI.getOpcode() == Hexagon::L2_loadrb_io) || (MI.getOpcode() == Hexagon::L2_loadrub_io) || (MI.getOpcode() == Hexagon::LDriw_f) || (MI.getOpcode() == Hexagon::LDrid_f)) { diff --git a/test/CodeGen/Hexagon/cext-check.ll b/test/CodeGen/Hexagon/cext-check.ll index 7c4b19e5a40..bad51cf3b94 100644 --- a/test/CodeGen/Hexagon/cext-check.ll +++ b/test/CodeGen/Hexagon/cext-check.ll @@ -29,9 +29,9 @@ return: } define i32 @cext_test2(i8* %a) nounwind { -; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+##1023) +; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+{{ *}}##1023) ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000) -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+##1024) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}##1024) ; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##6000) entry: %tobool = icmp ne i8* %a, null diff --git a/test/MC/Disassembler/Hexagon/ld.txt b/test/MC/Disassembler/Hexagon/ld.txt index aa66245ba92..3dd71eb1ceb 100644 --- a/test/MC/Disassembler/Hexagon/ld.txt +++ b/test/MC/Disassembler/Hexagon/ld.txt @@ -1,5 +1,17 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +0xf1 0xc3 0x15 0x91 +# CHECK: r17 = memb(r21 + #31) +0x91 0xdd 0x15 0x41 +# CHECK: if (p3) r17 = memb(r21 + #44) +0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memb(r21 + #44) +0x91 0xdd 0x15 0x45 +# CHECK: if (!p3) r17 = memb(r21 + #44) +0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44) 0xf1 0xc3 0x35 0x91 # CHECK: r17 = memub(r21 + #31) 0xf1 0xdb 0x35 0x41 -- 2.34.1