From 9bf4590aaa26ebb5afdbec079daeee8e0b268b47 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 20 May 2013 15:02:01 +0000 Subject: [PATCH] R600/SI: Make fitsRegClass() operands const MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Michel Dänzer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIISelLowering.cpp | 2 +- lib/Target/R600/SIISelLowering.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 237999f8c56..a077a95cdbb 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -513,7 +513,7 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate, } /// \brief Does "Op" fit into register class "RegClass" ? -bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op, +bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op, unsigned RegClass) const { MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h index af0625f4b58..62dfeda6018 100644 --- a/lib/Target/R600/SIISelLowering.h +++ b/lib/Target/R600/SIISelLowering.h @@ -30,7 +30,8 @@ class SITargetLowering : public AMDGPUTargetLowering { bool foldImm(SDValue &Operand, int32_t &Immediate, bool &ScalarSlotUsed) const; - bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const; + bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op, + unsigned RegClass) const; void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, unsigned RegClass, bool &ScalarSlotUsed) const; -- 2.34.1