From 9a68fdc7f8211a9330537d44e3406d79fc5562af Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Sat, 25 Feb 2012 03:37:25 +0000 Subject: [PATCH] Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 lowering for i386-*-win32 targets. Patch by Joe Groff. [Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems: Clang raised a warning, and X86 LowerOperation would assert out for fptoui f64 to i32 because it improperly lowered to an illegal BUILD_PAIR. Here's a patch that addresses these issues. Let me know if any other changes are necessary. Thanks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151432 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86FloatingPoint.cpp | 2 -- lib/Target/X86/X86ISelLowering.cpp | 27 ++++++++++++++++++--------- lib/Target/X86/X86ISelLowering.h | 3 ++- test/CodeGen/X86/win_ftol2.ll | 14 ++++++++++++++ 4 files changed, 34 insertions(+), 12 deletions(-) diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 5c003885419..32de194725c 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -1646,8 +1646,6 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { case X86::WIN_FTOL_32: case X86::WIN_FTOL_64: { - MachineBasicBlock::iterator InsertPt = MI; - // Push the operand into ST0. MachineOperand &Op = MI->getOperand(0); assert(Op.isUse() && Op.isReg() && diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 8cb8fbb369a..c1ecbbb83c0 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -7712,7 +7712,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, } std::pair X86TargetLowering:: -FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { +FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { DebugLoc DL = Op.getDebugLoc(); EVT DstTy = Op.getValueType(); @@ -7796,7 +7796,10 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { MVT::i32, ftol.getValue(1)); SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, MVT::i32, eax.getValue(2)); - SDValue pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, eax, edx); + SDValue Ops[] = { eax, edx }; + SDValue pair = IsReplace + ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) + : DAG.getMergeValues(Ops, 2, DL); return std::make_pair(pair, SDValue()); } } @@ -7806,7 +7809,8 @@ SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, if (Op.getValueType().isVector()) return SDValue(); - std::pair Vals = FP_TO_INTHelper(Op, DAG, true); + std::pair Vals = FP_TO_INTHelper(Op, DAG, + /*IsSigned=*/ true, /*IsReplace=*/ false); SDValue FIST = Vals.first, StackSlot = Vals.second; // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. if (FIST.getNode() == 0) return Op; @@ -7823,14 +7827,19 @@ SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const { - std::pair Vals = FP_TO_INTHelper(Op, DAG, false); + std::pair Vals = FP_TO_INTHelper(Op, DAG, + /*IsSigned=*/ false, /*IsReplace=*/ false); SDValue FIST = Vals.first, StackSlot = Vals.second; assert(FIST.getNode() && "Unexpected failure"); - // Load the result. - return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), - FIST, StackSlot, MachinePointerInfo(), - false, false, false, 0); + if (StackSlot.getNode()) + // Load the result. + return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), + FIST, StackSlot, MachinePointerInfo(), + false, false, false, 0); + else + // The node is the result. + return FIST; } SDValue X86TargetLowering::LowerFABS(SDValue Op, @@ -10872,7 +10881,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, return; std::pair Vals = - FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned); + FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); SDValue FIST = Vals.first, StackSlot = Vals.second; if (FIST.getNode() != 0) { EVT VT = N->getValueType(0); diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 8b6cda5927b..1f5657d30f3 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -708,7 +708,8 @@ namespace llvm { SelectionDAG &DAG) const; std::pair FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, - bool isSigned) const; + bool isSigned, + bool isReplace) const; SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, SelectionDAG &DAG) const; diff --git a/test/CodeGen/X86/win_ftol2.ll b/test/CodeGen/X86/win_ftol2.ll index 90d8a312eb6..596b4262e6b 100644 --- a/test/CodeGen/X86/win_ftol2.ll +++ b/test/CodeGen/X86/win_ftol2.ll @@ -128,3 +128,17 @@ define {double, i64} @double_ui64_4(double %x, double %y) nounwind { %5 = insertvalue {double, i64} %4, i64 %3, 1 ret {double, i64} %5 } + +define i32 @double_ui32_5(double %X) { +; FTOL: @double_ui32_5 +; FTOL: calll __ftol2 + %tmp.1 = fptoui double %X to i32 + ret i32 %tmp.1 +} + +define i64 @double_ui64_5(double %X) { +; FTOL: @double_ui64_5 +; FTOL: calll __ftol2 + %tmp.1 = fptoui double %X to i64 + ret i64 %tmp.1 +} -- 2.34.1