From 98107ffd1e5bb8d99d1e72995330b667a1018cf7 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 2 Jun 2004 06:06:20 +0000 Subject: [PATCH] Adjust to the new TargetMachine interface git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13957 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/InstrSched/InstrScheduling.cpp | 8 +++---- lib/CodeGen/InstrSched/SchedGraph.cpp | 24 +++++++++---------- .../SparcV9/InstrSched/InstrScheduling.cpp | 8 +++---- lib/Target/SparcV9/InstrSched/SchedGraph.cpp | 24 +++++++++---------- 4 files changed, 32 insertions(+), 32 deletions(-) diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index 63062691915..c95cce0b462 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -512,15 +512,15 @@ private: SchedulingManager::SchedulingManager(const TargetMachine& target, const SchedGraph* graph, SchedPriorities& _schedPrio) - : nslots(target.getSchedInfo().getMaxNumIssueTotal()), - schedInfo(target.getSchedInfo()), + : nslots(target.getSchedInfo()->getMaxNumIssueTotal()), + schedInfo(*target.getSchedInfo()), schedPrio(_schedPrio), isched(nslots, graph->getNumNodes()), totalInstrCount(graph->getNumNodes() - 2), nextEarliestIssueTime(0), choicesForSlot(nslots), - numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0 - nextEarliestStartTime(target.getInstrInfo().getNumOpcodes(), + numInClass(target.getSchedInfo()->getNumSchedClasses(), 0), // set all to 0 + nextEarliestStartTime(target.getInstrInfo()->getNumOpcodes(), (cycles_t) 0) // set all to 0 { updateTime(0); diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index 443f4e2c62a..e88c801a425 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -60,9 +60,9 @@ SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb, MI = I; MachineOpCode mopCode = MI->getOpcode(); - latency = Target.getInstrInfo().hasResultInterlock(mopCode) - ? Target.getInstrInfo().minLatency(mopCode) - : Target.getInstrInfo().maxLatency(mopCode); + latency = Target.getInstrInfo()->hasResultInterlock(mopCode) + ? Target.getInstrInfo()->minLatency(mopCode) + : Target.getInstrInfo()->maxLatency(mopCode); } } @@ -138,7 +138,7 @@ void SchedGraph::addDummyEdges() { void SchedGraph::addCDEdges(const TerminatorInst* term, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term); // Find the first branch instr in the sequence of machine instrs for term @@ -240,7 +240,7 @@ static const unsigned int SG_DepOrderArray[][3] = { // void SchedGraph::addMemEdges(const std::vector& memNodeVec, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, // so simply look at all pairs i]>. @@ -272,7 +272,7 @@ void SchedGraph::addMemEdges(const std::vector& memNodeVec, // void SchedGraph::addCallDepEdges(const std::vector& callDepNodeVec, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, // so simply look at all pairs i]>. @@ -471,7 +471,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, std::vector& callDepNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); MachineOpCode opCode = node->getOpcode(); @@ -493,7 +493,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, unsigned regNum = mop.getReg(); // If this is not a dummy zero register, record the reference in order - if (regNum != target.getRegInfo().getZeroRegNum()) + if (regNum != target.getRegInfo()->getZeroRegNum()) regToRefVecMap[mop.getReg()] .push_back(std::make_pair(node, i)); @@ -502,8 +502,8 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node) { unsigned rcid; - int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid); - if (target.getRegInfo().getMachineRegClass(rcid) + int regInClass = target.getRegInfo()->getClassRegNum(regNum, rcid); + if (target.getRegInfo()->getMachineRegClass(rcid) ->isRegVolatile(regInClass)) callDepNodeVec.push_back(node); } @@ -532,7 +532,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, const MachineOperand& mop = MI.getImplicitOp(i); if (mop.hasAllocatedReg()) { unsigned regNum = mop.getReg(); - if (regNum != target.getRegInfo().getZeroRegNum()) + if (regNum != target.getRegInfo()->getZeroRegNum()) regToRefVecMap[mop.getReg()] .push_back(std::make_pair(node, i + MI.getNumOperands())); continue; // nothing more to do @@ -553,7 +553,7 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target, std::vector& callDepNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Build graph nodes for each VM instruction and gather def/use info. // Do both those together in a single pass over all machine instructions. diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index 63062691915..c95cce0b462 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -512,15 +512,15 @@ private: SchedulingManager::SchedulingManager(const TargetMachine& target, const SchedGraph* graph, SchedPriorities& _schedPrio) - : nslots(target.getSchedInfo().getMaxNumIssueTotal()), - schedInfo(target.getSchedInfo()), + : nslots(target.getSchedInfo()->getMaxNumIssueTotal()), + schedInfo(*target.getSchedInfo()), schedPrio(_schedPrio), isched(nslots, graph->getNumNodes()), totalInstrCount(graph->getNumNodes() - 2), nextEarliestIssueTime(0), choicesForSlot(nslots), - numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0 - nextEarliestStartTime(target.getInstrInfo().getNumOpcodes(), + numInClass(target.getSchedInfo()->getNumSchedClasses(), 0), // set all to 0 + nextEarliestStartTime(target.getInstrInfo()->getNumOpcodes(), (cycles_t) 0) // set all to 0 { updateTime(0); diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index 443f4e2c62a..e88c801a425 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -60,9 +60,9 @@ SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb, MI = I; MachineOpCode mopCode = MI->getOpcode(); - latency = Target.getInstrInfo().hasResultInterlock(mopCode) - ? Target.getInstrInfo().minLatency(mopCode) - : Target.getInstrInfo().maxLatency(mopCode); + latency = Target.getInstrInfo()->hasResultInterlock(mopCode) + ? Target.getInstrInfo()->minLatency(mopCode) + : Target.getInstrInfo()->maxLatency(mopCode); } } @@ -138,7 +138,7 @@ void SchedGraph::addDummyEdges() { void SchedGraph::addCDEdges(const TerminatorInst* term, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term); // Find the first branch instr in the sequence of machine instrs for term @@ -240,7 +240,7 @@ static const unsigned int SG_DepOrderArray[][3] = { // void SchedGraph::addMemEdges(const std::vector& memNodeVec, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, // so simply look at all pairs i]>. @@ -272,7 +272,7 @@ void SchedGraph::addMemEdges(const std::vector& memNodeVec, // void SchedGraph::addCallDepEdges(const std::vector& callDepNodeVec, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, // so simply look at all pairs i]>. @@ -471,7 +471,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, std::vector& callDepNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); MachineOpCode opCode = node->getOpcode(); @@ -493,7 +493,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, unsigned regNum = mop.getReg(); // If this is not a dummy zero register, record the reference in order - if (regNum != target.getRegInfo().getZeroRegNum()) + if (regNum != target.getRegInfo()->getZeroRegNum()) regToRefVecMap[mop.getReg()] .push_back(std::make_pair(node, i)); @@ -502,8 +502,8 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node) { unsigned rcid; - int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid); - if (target.getRegInfo().getMachineRegClass(rcid) + int regInClass = target.getRegInfo()->getClassRegNum(regNum, rcid); + if (target.getRegInfo()->getMachineRegClass(rcid) ->isRegVolatile(regInClass)) callDepNodeVec.push_back(node); } @@ -532,7 +532,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, const MachineOperand& mop = MI.getImplicitOp(i); if (mop.hasAllocatedReg()) { unsigned regNum = mop.getReg(); - if (regNum != target.getRegInfo().getZeroRegNum()) + if (regNum != target.getRegInfo()->getZeroRegNum()) regToRefVecMap[mop.getReg()] .push_back(std::make_pair(node, i + MI.getNumOperands())); continue; // nothing more to do @@ -553,7 +553,7 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target, std::vector& callDepNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Build graph nodes for each VM instruction and gather def/use info. // Do both those together in a single pass over all machine instructions. -- 2.34.1