From 971f0f0071c7fc171a29978ea8a1fb5c4153e196 Mon Sep 17 00:00:00 2001 From: Michel Danzer Date: Fri, 6 Feb 2015 02:51:25 +0000 Subject: [PATCH] R600/SI: Don't enable WQM for V_INTERP_* instructions v2 Doesn't seem necessary anymore. I think this was mostly compensating for not enabling WQM for texture sampling instructions. v2: Add test coverage Reviewed-by: Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228373 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SILowerControlFlow.cpp | 6 ---- .../R600/llvm.SI.fs.interp.constant.ll | 22 -------------- test/CodeGen/R600/llvm.SI.fs.interp.ll | 30 +++++++++++++++++++ 3 files changed, 30 insertions(+), 28 deletions(-) delete mode 100644 test/CodeGen/R600/llvm.SI.fs.interp.constant.ll create mode 100644 test/CodeGen/R600/llvm.SI.fs.interp.ll diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp index f014f2e63de..2e08c9f5a5d 100644 --- a/lib/Target/R600/SILowerControlFlow.cpp +++ b/lib/Target/R600/SILowerControlFlow.cpp @@ -513,12 +513,6 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { case AMDGPU::SI_INDIRECT_DST_V16: IndirectDst(MI); break; - - case AMDGPU::V_INTERP_P1_F32: - case AMDGPU::V_INTERP_P2_F32: - case AMDGPU::V_INTERP_MOV_F32: - NeedWQM = true; - break; } } } diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll deleted file mode 100644 index 409d46dad5a..00000000000 --- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll +++ /dev/null @@ -1,22 +0,0 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s - -;CHECK: s_mov_b32 -;CHECK-NEXT: v_interp_mov_f32 - -define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { -main_body: - %4 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) - %5 = call i32 @llvm.SI.packf16(float %4, float %4) - %6 = bitcast i32 %5 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %6, float %6, float %6) - ret void -} - -declare void @llvm.AMDGPU.shader.type(i32) - -declare float @llvm.SI.fs.constant(i32, i32, i32) readnone - -declare i32 @llvm.SI.packf16(float, float) readnone - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.ll b/test/CodeGen/R600/llvm.SI.fs.interp.ll new file mode 100644 index 00000000000..6b36140b06c --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.fs.interp.ll @@ -0,0 +1,30 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s + +;CHECK-NOT: s_wqm +;CHECK: s_mov_b32 +;CHECK-NEXT: v_interp_mov_f32 +;CHECK: v_interp_p1_f32 +;CHECK: v_interp_p2_f32 + +define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 { +main_body: + %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) + %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4) + %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4) + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7) + ret void +} + +declare void @llvm.AMDGPU.shader.type(i32) + +; Function Attrs: nounwind readnone +declare float @llvm.SI.fs.constant(i32, i32, i32) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { nounwind readnone } -- 2.34.1