From 94a88c49b0e87ee8c911669ff6c6bbd31b912542 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 8 Aug 2013 21:37:32 +0000 Subject: [PATCH] [mips] Delete register class HWRegs64. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 39 --------------------- lib/Target/Mips/Mips64InstrInfo.td | 2 +- lib/Target/Mips/MipsRegisterInfo.cpp | 1 - lib/Target/Mips/MipsRegisterInfo.td | 11 ------ lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 6 ++-- 5 files changed, 3 insertions(+), 56 deletions(-) diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 3dd65623c71..c14f907ac69 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -96,9 +96,6 @@ class MipsAsmParser : public MCTargetAsmParser { MipsAsmParser::OperandMatchResultTy parseHWRegs(SmallVectorImpl &Operands); - MipsAsmParser::OperandMatchResultTy - parseHW64Regs(SmallVectorImpl &Operands); - MipsAsmParser::OperandMatchResultTy parseCCRRegs(SmallVectorImpl &Operands); @@ -221,7 +218,6 @@ public: Kind_GPR32, Kind_GPR64, Kind_HWRegs, - Kind_HW64Regs, Kind_FGR32Regs, Kind_FGR64Regs, Kind_AFGR64Regs, @@ -388,11 +384,6 @@ public: return Reg.Kind == Kind_HWRegs; } - bool isHW64RegsAsm() const { - assert((Kind == k_Register) && "Invalid access!"); - return Reg.Kind == Kind_HW64Regs; - } - bool isCCRAsm() const { assert((Kind == k_Register) && "Invalid access!"); return Reg.Kind == Kind_CCRRegs; @@ -1497,36 +1488,6 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl &Operands) { return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy -MipsAsmParser::parseHW64Regs( - SmallVectorImpl &Operands) { - - if (!isMips64()) - return MatchOperand_NoMatch; - // If the first token is not '$' we have an error. - if (Parser.getTok().isNot(AsmToken::Dollar)) - return MatchOperand_NoMatch; - SMLoc S = Parser.getTok().getLoc(); - Parser.Lex(); // Eat $ - - const AsmToken &Tok = Parser.getTok(); // Get the next token. - if (Tok.isNot(AsmToken::Integer)) - return MatchOperand_NoMatch; - - unsigned RegNum = Tok.getIntVal(); - // At the moment only hwreg29 is supported. - if (RegNum != 29) - return MatchOperand_ParseFail; - - MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S, - Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_HW64Regs); - Operands.push_back(op); - - Parser.Lex(); // Eat the register number. - return MatchOperand_Success; -} - MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseCCRRegs(SmallVectorImpl &Operands) { // If the first token is not '$' we have an error. diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index a752ab81e5c..ddc550b57ff 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -224,7 +224,7 @@ def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>; def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd, mem_ea_64>, LW_FM<0x19>; let isCodeGenOnly = 1 in -def RDHWR64 : ReadHardware, RDHWR_FM; +def RDHWR64 : ReadHardware, RDHWR_FM; def DEXT : ExtBase<"dext", GPR64Opnd>, EXT_FM<3>; let Pattern = [] in { diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 0b5fc33d800..eb1e056dca1 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -146,7 +146,6 @@ getReservedRegs(const MachineFunction &MF) const { // Reserve hardware registers. Reserved.set(Mips::HWR29); - Reserved.set(Mips::HWR29_64); // Reserve DSP control register. Reserved.set(Mips::DSPPos); diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index c72c30dc891..377f1aa1c21 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -190,7 +190,6 @@ let Namespace = "Mips" in { // Hardware register $29 def HWR29 : MipsReg<29, "29">; - def HWR29_64 : MipsReg<29, "29">; // Accum registers def AC0 : ACC<0, "ac0", [LO, HI]>; @@ -313,7 +312,6 @@ def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>; // Hardware registers def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; -def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable; // Accumulator Registers def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> { @@ -392,19 +390,10 @@ def HWRegsAsmOperand : MipsAsmRegOperand { let ParserMethod = "parseHWRegs"; } -def HW64RegsAsmOperand : MipsAsmRegOperand { - let Name = "HW64RegsAsm"; - let ParserMethod = "parseHW64Regs"; -} - def HWRegsOpnd : RegisterOperand { let ParserMatchClass = HWRegsAsmOperand; } -def HW64RegsOpnd : RegisterOperand { - let ParserMatchClass = HW64RegsAsmOperand; -} - def AFGR64RegsOpnd : RegisterOperand { let ParserMatchClass = AFGR64AsmOperand; } diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 3b6480a86fe..49da7846bf7 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -403,22 +403,20 @@ std::pair MipsSEDAGToDAGISel::selectNode(SDNode *Node) { case MipsISD::ThreadPointer: { EVT PtrVT = getTargetLowering()->getPointerTy(); - unsigned RdhwrOpc, SrcReg, DestReg; + unsigned RdhwrOpc, DestReg; if (PtrVT == MVT::i32) { RdhwrOpc = Mips::RDHWR; - SrcReg = Mips::HWR29; DestReg = Mips::V1; } else { RdhwrOpc = Mips::RDHWR64; - SrcReg = Mips::HWR29_64; DestReg = Mips::V1_64; } SDNode *Rdhwr = CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node), Node->getValueType(0), - CurDAG->getRegister(SrcReg, PtrVT)); + CurDAG->getRegister(Mips::HWR29, MVT::i32)); SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, SDValue(Rdhwr, 0)); SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT); -- 2.34.1