From 92fca73d521758012e0e425eac33bb77e888112e Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Mon, 17 Mar 2014 19:36:09 +0000 Subject: [PATCH] Switch a number of loops in lib/CodeGen over to range-based for-loops, now that the MachineRegisterInfo iterators are compatible with it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204075 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/LiveDebugVariables.cpp | 8 +++--- lib/CodeGen/LiveRangeCalc.cpp | 18 ++++++-------- lib/CodeGen/LiveRangeEdit.cpp | 6 ++--- lib/CodeGen/MachineCSE.cpp | 26 +++++++------------- lib/CodeGen/MachineLICM.cpp | 30 +++++++++-------------- lib/CodeGen/MachineRegisterInfo.cpp | 20 +++++++-------- lib/CodeGen/MachineSink.cpp | 27 +++++++++----------- lib/CodeGen/OptimizePHIs.cpp | 6 ++--- lib/CodeGen/PHIElimination.cpp | 6 ++--- lib/CodeGen/PHIEliminationUtils.cpp | 8 +++--- lib/CodeGen/PeepholeOptimizer.cpp | 19 +++++--------- lib/CodeGen/ProcessImplicitDefs.cpp | 5 +--- lib/CodeGen/RegisterCoalescer.cpp | 14 ++++------- lib/CodeGen/SplitKit.cpp | 8 +++--- lib/CodeGen/TailDuplication.cpp | 8 +++--- lib/CodeGen/TwoAddressInstructionPass.cpp | 16 +++++------- lib/CodeGen/VirtRegMap.cpp | 6 ++--- 17 files changed, 88 insertions(+), 143 deletions(-) diff --git a/lib/CodeGen/LiveDebugVariables.cpp b/lib/CodeGen/LiveDebugVariables.cpp index 317f54461eb..bef41563eab 100644 --- a/lib/CodeGen/LiveDebugVariables.cpp +++ b/lib/CodeGen/LiveDebugVariables.cpp @@ -568,12 +568,10 @@ UserValue::addDefsFromCopies(LiveInterval *LI, unsigned LocNo, // Collect all the (vreg, valno) pairs that are copies of LI. SmallVector, 8> CopyValues; - for (MachineRegisterInfo::use_nodbg_iterator - UI = MRI.use_nodbg_begin(LI->reg), - UE = MRI.use_nodbg_end(); UI != UE; ++UI) { - MachineInstr *MI = UI->getParent(); + for (MachineOperand &MO : MRI.use_nodbg_operands(LI->reg)) { + MachineInstr *MI = MO.getParent(); // Copies of the full value. - if (UI->getSubReg() || !MI->isCopy()) + if (MO.getSubReg() || !MI->isCopy()) continue; unsigned DstReg = MI->getOperand(0).getReg(); diff --git a/lib/CodeGen/LiveRangeCalc.cpp b/lib/CodeGen/LiveRangeCalc.cpp index 4c7723c38f2..ecd75b4ffaa 100644 --- a/lib/CodeGen/LiveRangeCalc.cpp +++ b/lib/CodeGen/LiveRangeCalc.cpp @@ -41,9 +41,8 @@ void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { // Visit all def operands. If the same instruction has multiple defs of Reg, // LR.createDeadDef() will deduplicate. - for (MachineRegisterInfo::def_iterator - I = MRI->def_begin(Reg), E = MRI->def_end(); I != E; ++I) { - const MachineInstr *MI = I->getParent(); + for (MachineOperand &MO : MRI->def_operands(Reg)) { + const MachineInstr *MI = MO.getParent(); // Find the corresponding slot index. SlotIndex Idx; if (MI->isPHI()) @@ -52,7 +51,7 @@ void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { else // Instructions are either normal 'r', or early clobber 'e'. Idx = Indexes->getInstructionIndex(MI) - .getRegSlot(I->isEarlyClobber()); + .getRegSlot(MO.isEarlyClobber()); // Create the def in LR. This may find an existing def. LR.createDeadDef(Idx, *Alloc); @@ -64,9 +63,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { assert(MRI && Indexes && "call reset() first"); // Visit all operands that read Reg. This may include partial defs. - for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg), - E = MRI->reg_nodbg_end(); I != E; ++I) { - MachineOperand &MO = *I; + for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) { // Clear all kill flags. They will be reinserted after register allocation // by LiveIntervalAnalysis::addKillFlags(). if (MO.isUse()) @@ -75,7 +72,8 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { continue; // MI is reading Reg. We may have visited MI before if it happens to be // reading Reg multiple times. That is OK, extend() is idempotent. - const MachineInstr *MI = I->getParent(); + const MachineInstr *MI = MO.getParent(); + unsigned OpNo = (&MO - &MI->getOperand(0)); // Find the SlotIndex being read. SlotIndex Idx; @@ -83,7 +81,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { assert(!MO.isDef() && "Cannot handle PHI def of partial register."); // PHI operands are paired: (Reg, PredMBB). // Extend the live range to be live-out from PredMBB. - Idx = Indexes->getMBBEndIdx(MI->getOperand(I.getOperandNo()+1).getMBB()); + Idx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); } else { // This is a normal instruction. Idx = Indexes->getInstructionIndex(MI).getRegSlot(); @@ -92,7 +90,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { if (MO.isDef()) { if (MO.isEarlyClobber()) Idx = Idx.getRegSlot(true); - } else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) { + } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { // FIXME: This would be a lot easier if tied early-clobber uses also // had an early-clobber flag. if (MI->getOperand(DefIdx).isEarlyClobber()) diff --git a/lib/CodeGen/LiveRangeEdit.cpp b/lib/CodeGen/LiveRangeEdit.cpp index c7372592854..891eaab1a59 100644 --- a/lib/CodeGen/LiveRangeEdit.cpp +++ b/lib/CodeGen/LiveRangeEdit.cpp @@ -167,10 +167,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI, MachineInstr *DefMI = 0, *UseMI = 0; // Check that there is a single def and a single use. - for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg), - E = MRI.reg_nodbg_end(); I != E; ++I) { - MachineOperand &MO = *I; - MachineInstr *MI = I->getParent(); + for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) { + MachineInstr *MI = MO.getParent(); if (MO.isDef()) { if (DefMI && DefMI != MI) return false; diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index 76ab7dcb6a3..fd153d8c448 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -364,15 +364,11 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, TargetRegisterInfo::isVirtualRegister(Reg)) { MayIncreasePressure = false; SmallPtrSet CSUses; - for (MachineRegisterInfo::use_instr_nodbg_iterator - I = MRI->use_instr_nodbg_begin(CSReg), E = MRI->use_instr_nodbg_end(); - I != E; ++I) { - CSUses.insert(&*I); + for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) { + CSUses.insert(&MI); } - for (MachineRegisterInfo::use_instr_nodbg_iterator - I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); - I != E; ++I) { - if (!CSUses.count(&*I)) { + for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { + if (!CSUses.count(&MI)) { MayIncreasePressure = true; break; } @@ -403,11 +399,9 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, } if (!HasVRegUse) { bool HasNonCopyUse = false; - for (MachineRegisterInfo::use_instr_nodbg_iterator - I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); - I != E; ++I) { + for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { // Ignore copies. - if (!I->isCopyLike()) { + if (!MI.isCopyLike()) { HasNonCopyUse = true; break; } @@ -420,11 +414,9 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, // it unless the defined value is already used in the BB of the new use. bool HasPHI = false; SmallPtrSet CSBBs; - for (MachineRegisterInfo::use_instr_nodbg_iterator - I = MRI->use_instr_nodbg_begin(CSReg), E = MRI->use_instr_nodbg_end(); - I != E; ++I) { - HasPHI |= I->isPHI(); - CSBBs.insert(I->getParent()); + for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) { + HasPHI |= MI.isPHI(); + CSBBs.insert(MI.getParent()); } if (!HasPHI) diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 9fcf11396fa..08678f81da5 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -978,26 +978,23 @@ bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const { unsigned Reg = MO->getReg(); if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; - for (MachineRegisterInfo::use_instr_iterator - UI = MRI->use_instr_begin(Reg), UE = MRI->use_instr_end(); - UI != UE; ++UI) { - MachineInstr *UseMI = &*UI; + for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { // A PHI may cause a copy to be inserted. - if (UseMI->isPHI()) { + if (UseMI.isPHI()) { // A PHI inside the loop causes a copy because the live range of Reg is // extended across the PHI. - if (CurLoop->contains(UseMI)) + if (CurLoop->contains(&UseMI)) return true; // A PHI in an exit block can cause a copy to be inserted if the PHI // has multiple predecessors in the loop with different values. // For now, approximate by rejecting all exit blocks. - if (isExitBlock(UseMI->getParent())) + if (isExitBlock(UseMI.getParent())) return true; continue; } // Look past copies as well. - if (UseMI->isCopy() && CurLoop->contains(UseMI)) - Work.push_back(UseMI); + if (UseMI.isCopy() && CurLoop->contains(&UseMI)) + Work.push_back(&UseMI); } } } while (!Work.empty()); @@ -1012,23 +1009,20 @@ bool MachineLICM::HasHighOperandLatency(MachineInstr &MI, if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg)) return false; - for (MachineRegisterInfo::use_instr_nodbg_iterator - I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); - I != E; ++I) { - MachineInstr *UseMI = &*I; - if (UseMI->isCopyLike()) + for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { + if (UseMI.isCopyLike()) continue; - if (!CurLoop->contains(UseMI->getParent())) + if (!CurLoop->contains(UseMI.getParent())) continue; - for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = UseMI->getOperand(i); + for (unsigned i = 0, e = UseMI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = UseMI.getOperand(i); if (!MO.isReg() || !MO.isUse()) continue; unsigned MOReg = MO.getReg(); if (MOReg != Reg) continue; - if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i)) + if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, &UseMI, i)) return true; } diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index 094cf84dd3a..db3eec36746 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -77,11 +77,11 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { return false; // Accumulate constraints from all uses. - for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; - ++I) { + for (MachineOperand &MO : reg_nodbg_operands(Reg)) { // Apply the effect of the given operand to NewRC. - MachineInstr *MI = I->getParent(); - NewRC = MI->getRegClassConstraintEffect(I.getOperandNo(), NewRC, TII, + MachineInstr *MI = MO.getParent(); + unsigned OpNo = &MO - &MI->getOperand(0); + NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, getTargetRegisterInfo()); if (!NewRC || NewRC == OldRC) return false; @@ -126,8 +126,8 @@ void MachineRegisterInfo::clearVirtRegs() { void MachineRegisterInfo::verifyUseList(unsigned Reg) const { #ifndef NDEBUG bool Valid = true; - for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) { - MachineOperand *MO = &*I; + for (MachineOperand &M : reg_operands(Reg)) { + MachineOperand *MO = &M; MachineInstr *MI = MO->getParent(); if (!MI) { errs() << PrintReg(Reg, getTargetRegisterInfo()) @@ -329,8 +329,8 @@ bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { /// optimization passes which extend register lifetimes and need only /// preserve conservative kill flag information. void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { - for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) - UI->setIsKill(false); + for (MachineOperand &MO : use_operands(Reg)) + MO.setIsKill(false); } bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { @@ -392,8 +392,8 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, #ifndef NDEBUG void MachineRegisterInfo::dumpUses(unsigned Reg) const { - for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) - I->getParent()->dump(); + for (MachineInstr &I : use_instructions(Reg)) + I.dump(); } #endif diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index 4523753eba5..e9e97cc2379 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -171,13 +171,12 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, // Predecessors according to CFG: BB#0 BB#1 // %reg16386 = PHI %reg16434, , %reg16385, BreakPHIEdge = true; - for (MachineRegisterInfo::use_nodbg_iterator - I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); - I != E; ++I) { - MachineInstr *UseInst = I->getParent(); + for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { + MachineInstr *UseInst = MO.getParent(); + unsigned OpNo = &MO - &UseInst->getOperand(0); MachineBasicBlock *UseBlock = UseInst->getParent(); if (!(UseBlock == MBB && UseInst->isPHI() && - UseInst->getOperand(I.getOperandNo()+1).getMBB() == DefMBB)) { + UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) { BreakPHIEdge = false; break; } @@ -185,16 +184,15 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, if (BreakPHIEdge) return true; - for (MachineRegisterInfo::use_nodbg_iterator - I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); - I != E; ++I) { + for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { // Determine the block of the use. - MachineInstr *UseInst = I->getParent(); + MachineInstr *UseInst = MO.getParent(); + unsigned OpNo = &MO - &UseInst->getOperand(0); MachineBasicBlock *UseBlock = UseInst->getParent(); if (UseInst->isPHI()) { // PHI nodes use the operand in the predecessor block, not the block with // the PHI. - UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB(); + UseBlock = UseInst->getOperand(OpNo+1).getMBB(); } else if (UseBlock == DefMBB) { LocalUse = true; return false; @@ -450,12 +448,9 @@ bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, // Check if only use in post dominated block is PHI instruction. bool NonPHIUse = false; - for (MachineRegisterInfo::use_instr_nodbg_iterator - I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); - I != E; ++I) { - MachineInstr *UseInst = &*I; - MachineBasicBlock *UseBlock = UseInst->getParent(); - if (UseBlock == SuccToSinkTo && !UseInst->isPHI()) + for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) { + MachineBasicBlock *UseBlock = UseInst.getParent(); + if (UseBlock == SuccToSinkTo && !UseInst.isPHI()) NonPHIUse = true; } if (!NonPHIUse) diff --git a/lib/CodeGen/OptimizePHIs.cpp b/lib/CodeGen/OptimizePHIs.cpp index 50968efc9d5..4973802aa05 100644 --- a/lib/CodeGen/OptimizePHIs.cpp +++ b/lib/CodeGen/OptimizePHIs.cpp @@ -139,10 +139,8 @@ bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) { if (PHIsInCycle.size() == 16) return false; - for (MachineRegisterInfo::use_instr_iterator I = MRI->use_instr_begin(DstReg), - E = MRI->use_instr_end(); I != E; ++I) { - MachineInstr *UseMI = &*I; - if (!UseMI->isPHI() || !IsDeadPHICycle(UseMI, PHIsInCycle)) + for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { + if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle)) return false; } diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index cff80317d13..0e9df584847 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -198,10 +198,8 @@ bool PHIElimination::EliminatePHINodes(MachineFunction &MF, /// This includes registers with no defs. static bool isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI) { - for (MachineRegisterInfo::def_instr_iterator - DI = MRI->def_instr_begin(VirtReg), DE = MRI->def_instr_end(); - DI != DE; ++DI) - if (!DI->isImplicitDef()) + for (MachineInstr &DI : MRI->def_instructions(VirtReg)) + if (!DI.isImplicitDef()) return false; return true; } diff --git a/lib/CodeGen/PHIEliminationUtils.cpp b/lib/CodeGen/PHIEliminationUtils.cpp index 14cb94b05ba..99bbad1cc28 100644 --- a/lib/CodeGen/PHIEliminationUtils.cpp +++ b/lib/CodeGen/PHIEliminationUtils.cpp @@ -34,11 +34,9 @@ llvm::findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB, // Discover any defs/uses in this basic block. SmallPtrSet DefUsesInMBB; MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); - for (MachineRegisterInfo::reg_instr_iterator - RI = MRI.reg_instr_begin(SrcReg), RE = MRI.reg_instr_end(); - RI != RE; ++RI) { - if (RI->getParent() == MBB) - DefUsesInMBB.insert(&*RI); + for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) { + if (RI.getParent() == MBB) + DefUsesInMBB.insert(&RI); } MachineBasicBlock::iterator InsertPoint; diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp index eac72599a2a..73c9e1ce1a8 100644 --- a/lib/CodeGen/PeepholeOptimizer.cpp +++ b/lib/CodeGen/PeepholeOptimizer.cpp @@ -187,10 +187,8 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, // The source has other uses. See if we can replace the other uses with use of // the result of the extension. SmallPtrSet ReachedBBs; - for (MachineRegisterInfo::use_instr_nodbg_iterator - UI = MRI->use_instr_nodbg_begin(DstReg), UE = MRI->use_instr_nodbg_end(); - UI != UE; ++UI) - ReachedBBs.insert(UI->getParent()); + for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) + ReachedBBs.insert(UI.getParent()); // Uses that are in the same BB of uses of the result of the instruction. SmallVector Uses; @@ -199,10 +197,7 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, SmallVector ExtendedUses; bool ExtendLife = true; - for (MachineRegisterInfo::use_nodbg_iterator - UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); - UI != UE; ++UI) { - MachineOperand &UseMO = *UI; + for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) { MachineInstr *UseMI = UseMO.getParent(); if (UseMI == MI) continue; @@ -270,11 +265,9 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, // Look for PHI uses of the extended result, we don't want to extend the // liveness of a PHI input. It breaks all kinds of assumptions down // stream. A PHI use is expected to be the kill of its source values. - for (MachineRegisterInfo::use_instr_nodbg_iterator - UI = MRI->use_instr_nodbg_begin(DstReg), - UE = MRI->use_instr_nodbg_end(); UI != UE; ++UI) - if (UI->isPHI()) - PHIBBs.insert(UI->getParent()); + for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) + if (UI.isPHI()) + PHIBBs.insert(UI.getParent()); const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); for (unsigned i = 0, e = Uses.size(); i != e; ++i) { diff --git a/lib/CodeGen/ProcessImplicitDefs.cpp b/lib/CodeGen/ProcessImplicitDefs.cpp index 84503b5aab8..360e8d78084 100644 --- a/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/lib/CodeGen/ProcessImplicitDefs.cpp @@ -80,10 +80,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { if (TargetRegisterInfo::isVirtualRegister(Reg)) { // For virtual registers, mark all uses as , and convert users to // implicit-def when possible. - for (MachineRegisterInfo::use_nodbg_iterator UI = - MRI->use_nodbg_begin(Reg), - UE = MRI->use_nodbg_end(); UI != UE; ++UI) { - MachineOperand &MO = *UI; + for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { MO.setIsUndef(); MachineInstr *UserMI = MO.getParent(); if (!canTurnIntoImplicitDef(UserMI)) diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index 036a896791c..682c26c2c83 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -620,16 +620,15 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, // If some of the uses of IntA.reg is already coalesced away, return false. // It's not possible to determine whether it's safe to perform the coalescing. - for (MachineRegisterInfo::use_nodbg_iterator UI = - MRI->use_nodbg_begin(IntA.reg), - UE = MRI->use_nodbg_end(); UI != UE; ++UI) { - MachineInstr *UseMI = UI->getParent(); + for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) { + MachineInstr *UseMI = MO.getParent(); + unsigned OpNo = &MO - &UseMI->getOperand(0); SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); if (US == IntA.end() || US->valno != AValNo) continue; // If this use is tied to a def, we can't rewrite the register. - if (UseMI->isRegTiedToDefOperand(UI.getOperandNo())) + if (UseMI->isRegTiedToDefOperand(OpNo)) return false; } @@ -910,10 +909,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI, DstInt->removeValNo(DeadVNI); // Find new undef uses. - for (MachineRegisterInfo::reg_nodbg_iterator - I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end(); - I != E; ++I) { - MachineOperand &MO = *I; + for (MachineOperand &MO : MRI->reg_nodbg_operands(DstInt->reg)) { if (MO.isDef() || MO.isUndef()) continue; MachineInstr *MI = MO.getParent(); diff --git a/lib/CodeGen/SplitKit.cpp b/lib/CodeGen/SplitKit.cpp index 1e0f1e14d4a..16fe9790105 100644 --- a/lib/CodeGen/SplitKit.cpp +++ b/lib/CodeGen/SplitKit.cpp @@ -131,11 +131,9 @@ void SplitAnalysis::analyzeUses() { // Get use slots form the use-def chain. const MachineRegisterInfo &MRI = MF.getRegInfo(); - for (MachineRegisterInfo::use_nodbg_iterator - I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E; - ++I) - if (!I->isUndef()) - UseSlots.push_back(LIS.getInstructionIndex(I->getParent()).getRegSlot()); + for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg)) + if (!MO.isUndef()) + UseSlots.push_back(LIS.getInstructionIndex(MO.getParent()).getRegSlot()); array_pod_sort(UseSlots.begin(), UseSlots.end()); diff --git a/lib/CodeGen/TailDuplication.cpp b/lib/CodeGen/TailDuplication.cpp index df28c3938ad..40ce2b6cbba 100644 --- a/lib/CodeGen/TailDuplication.cpp +++ b/lib/CodeGen/TailDuplication.cpp @@ -338,12 +338,10 @@ bool TailDuplicatePass::TailDuplicateBlocks(MachineFunction &MF) { static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI) { - for (MachineRegisterInfo::use_instr_iterator UI = MRI->use_instr_begin(Reg), - UE = MRI->use_instr_end(); UI != UE; ++UI) { - MachineInstr *UseMI = &*UI; - if (UseMI->isDebugValue()) + for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { + if (UseMI.isDebugValue()) continue; - if (UseMI->getParent() != BB) + if (UseMI.getParent() != BB) return true; } return false; diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 4fbf068b671..d9e5aaedd9e 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -315,9 +315,7 @@ bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef) { LastDef = 0; unsigned LastUse = Dist; - for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), - E = MRI->reg_end(); I != E; ++I) { - MachineOperand &MO = *I; + for (MachineOperand &MO : MRI->reg_operands(Reg)) { MachineInstr *MI = MO.getParent(); if (MI->getParent() != MBB || MI->isDebugValue()) continue; @@ -914,19 +912,17 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, /// instruction too close to the defs of its register dependencies. bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI) { - for (MachineRegisterInfo::def_instr_iterator DI = MRI->def_instr_begin(Reg), - DE = MRI->def_instr_end(); DI != DE; ++DI) { - MachineInstr *DefMI = &*DI; - if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) + for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { + if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike()) continue; - if (DefMI == MI) + if (&DefMI == MI) return true; // MI is defining something KillMI uses - DenseMap::iterator DDI = DistanceMap.find(DefMI); + DenseMap::iterator DDI = DistanceMap.find(&DefMI); if (DDI == DistanceMap.end()) return true; // Below MI unsigned DefDist = DDI->second; assert(Dist > DefDist && "Visited def already?"); - if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) + if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist)) return true; } return false; diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 54bc6f8eb08..f892e94e54d 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -418,10 +418,8 @@ void VirtRegRewriter::rewrite() { // Check if this register has a use that will impact the rest of the // code. Uses in debug and noreturn instructions do not impact the // generated code. - for (MachineRegisterInfo::reg_instr_nodbg_iterator It = - MRI->reg_instr_nodbg_begin(Reg), - EndIt = MRI->reg_instr_nodbg_end(); It != EndIt; ++It) { - if (!NoReturnInsts.count(&(*It))) { + for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) { + if (!NoReturnInsts.count(&It)) { MRI->setPhysRegUsed(Reg); break; } -- 2.34.1