From 915eeb488786379250808d47668c43e010efe566 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Sun, 13 Feb 2011 09:10:56 +0000
Subject: [PATCH] when legalizing extremely wide shifts, make sure that the
 shift amounts are in a suitably wide type so that we don't generate out of
 range constant shift amounts.

This fixes PR9028.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125458 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp |  8 +++++++-
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp  |  4 ++--
 test/CodeGen/X86/crash.ll                         | 12 ++++++++++++
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 007f8d658e1..4c8cb5253a6 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1167,13 +1167,19 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
   unsigned NVTBits = NVT.getSizeInBits();
   EVT ShTy = N->getOperand(1).getValueType();
 
+  // If this is a large integer being legalized (e.g. an i512) then plop the
+  // shift amount down as a fixed i32.  The target shift amount may be something
+  // like i8, but this isn't enough to represent the shift amount.
+  if (NVTBits > 256)
+    ShTy = MVT::i32;
+  
   if (N->getOpcode() == ISD::SHL) {
     if (Amt > VTBits) {
       Lo = Hi = DAG.getConstant(0, NVT);
     } else if (Amt > NVTBits) {
       Lo = DAG.getConstant(0, NVT);
       Hi = DAG.getNode(ISD::SHL, dl,
-                       NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
+                       NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
     } else if (Amt == NVTBits) {
       Lo = DAG.getConstant(0, NVT);
       Hi = InL;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index d9faea12476..696cd24f0a7 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2426,11 +2426,11 @@ void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
   SDValue Op2 = getValue(I.getOperand(1));
   
   MVT ShiftTy = TLI.getShiftAmountTy();
-  unsigned ShiftSize = ShiftTy.getSizeInBits();
-  unsigned Op2Size = Op2.getValueType().getSizeInBits();
   
   // Coerce the shift amount to the right type if we can.
   if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
+    unsigned ShiftSize = ShiftTy.getSizeInBits();
+    unsigned Op2Size = Op2.getValueType().getSizeInBits();
     DebugLoc DL = getCurDebugLoc();
     
     // If the operand is smaller than the shift count type, promote it.
diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll
index 93277764963..2d8e63e3134 100644
--- a/test/CodeGen/X86/crash.ll
+++ b/test/CodeGen/X86/crash.ll
@@ -187,3 +187,15 @@ for.inc44:                                        ; preds = %for.body
   %add46 = add i32 %l_74.0, 1
   br label %for.body
 }
+
+; PR9028
+define void @f(i64 %A) nounwind {
+entry:
+  %0 = zext i64 %A to i160
+  %1 = shl i160 %0, 64
+  %2 = zext i160 %1 to i576
+  %3 = zext i96 undef to i576
+  %4 = or i576 %3, %2
+  store i576 %4, i576* undef, align 8
+  ret void
+}
-- 
2.34.1