From 8d7e5efcaa5a1625e9518d090697f08d6d1110d5 Mon Sep 17 00:00:00 2001
From: Jack Carter <jcarter@mips.com>
Date: Thu, 9 Aug 2012 19:43:18 +0000
Subject: [PATCH] Another 32 to 64 bit sign extension bug.

The fields in the td definition were switched.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/Mips64InstrInfo.td |  2 +-
 test/MC/Mips/sext_64_32.ll         | 13 +++++++++----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 5bebc4f2459..20fc1780775 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -220,7 +220,7 @@ def DEXT : ExtBase<3, "dext", CPU64Regs>;
 def DINS : InsBase<7, "dins", CPU64Regs>;
 
 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
-  def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+  def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
                      "dsll\t$rd, $rt, 32", [], IIAlu>;
   def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
                     "sll\t$rd, $rt, 0", [], IIAlu>;
diff --git a/test/MC/Mips/sext_64_32.ll b/test/MC/Mips/sext_64_32.ll
index bc0b5b184fd..e5c57b8c41d 100644
--- a/test/MC/Mips/sext_64_32.ll
+++ b/test/MC/Mips/sext_64_32.ll
@@ -4,12 +4,17 @@
 
 ; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0
 
-; ModuleID = '../sext.c'
-;target datalayout = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v64:64:64-n32"
-;target triple = "mips64el-unknown-linux"
-
 define i64 @foo(i32 %ival) nounwind readnone {
 entry:
   %conv = sext i32 %ival to i64
   ret i64 %conv
 }
+
+; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 0
+
+define i64 @foo_2(i32 %ival_2) nounwind readnone {
+entry:
+  %conv_2 = zext i32 %ival_2 to i64
+  ret i64 %conv_2
+}
+
-- 
2.34.1