From 8c9e52a9fc1f99cf80c499ef10e6c8a54ef899d4 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Wed, 10 Apr 2013 12:08:35 +0000 Subject: [PATCH] ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARM.td | 16 ++++++++---- lib/Target/ARM/ARMInstrInfo.td | 5 +++- lib/Target/ARM/ARMInstrThumb2.td | 3 ++- lib/Target/ARM/ARMSubtarget.cpp | 1 + lib/Target/ARM/ARMSubtarget.h | 4 +++ test/MC/ARM/arm-thumb-trustzone.s | 25 +++++++++++++++++++ test/MC/ARM/arm-trustzone.s | 24 ++++++++++++++++++ test/MC/ARM/basic-arm-instructions.s | 9 ------- .../Disassembler/ARM/arm-thumb-trustzone.txt | 17 +++++++++++++ test/MC/Disassembler/ARM/arm-trustzone.txt | 16 ++++++++++++ .../ARM/basic-arm-instructions.txt | 9 ------- 11 files changed, 104 insertions(+), 25 deletions(-) create mode 100644 test/MC/ARM/arm-thumb-trustzone.s create mode 100644 test/MC/ARM/arm-trustzone.s create mode 100644 test/MC/Disassembler/ARM/arm-thumb-trustzone.txt create mode 100644 test/MC/Disassembler/ARM/arm-trustzone.txt diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 68380847a02..2d7470919dc 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -59,6 +59,8 @@ def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", "FP compare + branch is slow">; def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", "Floating point unit supports single precision only">; +def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", + "Enable support for TrustZone security extensions">; // Some processors have FP multiply-accumulate instructions that don't // play nicely with other VFP / NEON instructions, and it's generally better @@ -144,29 +146,33 @@ include "ARMSchedule.td" def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", "Cortex-A5 ARM processors", [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, - FeatureVMLxForwarding, FeatureT2XtPk]>; + FeatureVMLxForwarding, FeatureT2XtPk, + FeatureTrustZone]>; def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", "Cortex-A8 ARM processors", [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, - FeatureVMLxForwarding, FeatureT2XtPk]>; + FeatureVMLxForwarding, FeatureT2XtPk, + FeatureTrustZone]>; def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", "Cortex-A9 ARM processors", [FeatureVMLxForwarding, FeatureT2XtPk, FeatureFP16, - FeatureAvoidPartialCPSR]>; + FeatureAvoidPartialCPSR, + FeatureTrustZone]>; def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", "Swift ARM processors", [FeatureNEONForFP, FeatureT2XtPk, FeatureVFP4, FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, - FeatureHasSlowFPVMLx]>; + FeatureHasSlowFPVMLx, FeatureTrustZone]>; // FIXME: It has not been determined if A15 has these features. def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", "Cortex-A15 ARM processors", [FeatureT2XtPk, FeatureFP16, - FeatureAvoidPartialCPSR]>; + FeatureAvoidPartialCPSR, + FeatureTrustZone]>; def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", [FeatureSlowFPBrcc, FeatureHWDivARM, diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 11550c5ae67..93c18ae2954 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -221,6 +221,9 @@ def HasDB : Predicate<"Subtarget->hasDataBarrier()">, def HasMP : Predicate<"Subtarget->hasMPExtension()">, AssemblerPredicate<"FeatureMP", "mp-extensions">; +def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, + AssemblerPredicate<"FeatureTrustZone", + "TrustZone">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; def IsThumb : Predicate<"Subtarget->isThumb()">, @@ -2077,7 +2080,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { // Secure Monitor Call is a system instruction. def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", - []> { + []>, Requires<[IsARM, HasTrustZone]> { bits<4> opt; let Inst{23-4} = 0b01100000000000000111; let Inst{3-0} = opt; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index c9d709eb522..4db37ca051f 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3449,7 +3449,8 @@ def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { // Secure Monitor Call is a system instruction. // Option = Inst{19-16} -def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> { +def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", + []>, Requires<[IsThumb2, HasTrustZone]> { let Inst{31-27} = 0b11110; let Inst{26-20} = 0b1111111; let Inst{15-12} = 0b1000; diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 739300e4eff..8653c462f06 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -91,6 +91,7 @@ void ARMSubtarget::initializeEnvironment() { HasRAS = false; HasMPExtension = false; FPOnlySP = false; + HasTrustZone = false; AllowsUnalignedMem = false; Thumb2DSP = false; UseNaClTrap = false; diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index 5b5ee6aeb86..038eb76ae1d 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -148,6 +148,9 @@ protected: /// precision. bool FPOnlySP; + /// HasTrustZone - if true, processor supports TrustZone security extensions + bool HasTrustZone; + /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory /// accesses for some types. For details, see /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). @@ -251,6 +254,7 @@ public: bool hasVMLxForwarding() const { return HasVMLxForwarding; } bool isFPBrccSlow() const { return SlowFPBrcc; } bool isFPOnlySP() const { return FPOnlySP; } + bool hasTrustZone() const { return HasTrustZone; } bool prefers32BitThumb() const { return Pref32BitThumb; } bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } diff --git a/test/MC/ARM/arm-thumb-trustzone.s b/test/MC/ARM/arm-thumb-trustzone.s new file mode 100644 index 00000000000..a080b3efac8 --- /dev/null +++ b/test/MC/ARM/arm-thumb-trustzone.s @@ -0,0 +1,25 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + .syntax unified + .globl _func + +@ Check that the assembler processes SMC instructions when TrustZone support is +@ active and that it rejects them when this feature is not enabled + +_func: +@ CHECK: _func + + +@------------------------------------------------------------------------------ +@ SMC +@------------------------------------------------------------------------------ + smc #0xf + ite eq + smceq #0 + +@ NOTZ-NOT: smc #15 +@ NOTZ-NOT: smceq #0 +@ TZ: smc #15 @ encoding: [0xff,0xf7,0x00,0x80] +@ TZ: ite eq @ encoding: [0x0c,0xbf] +@ TZ: smceq #0 @ encoding: [0xf0,0xf7,0x00,0x80] diff --git a/test/MC/ARM/arm-trustzone.s b/test/MC/ARM/arm-trustzone.s new file mode 100644 index 00000000000..69157f60dc0 --- /dev/null +++ b/test/MC/ARM/arm-trustzone.s @@ -0,0 +1,24 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + .syntax unified + .globl _func + +@ Check that the assembler processes SMC instructions when TrustZone support is +@ active and that it rejects them when this feature is not enabled + +_func: +@ CHECK: _func + + +@------------------------------------------------------------------------------ +@ SMC +@------------------------------------------------------------------------------ + smc #0xf + smceq #0 + +@ NOTZ-NOT: smc #15 +@ NOTZ-NOT: smceq #0 +@ TZ: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1] +@ TZ: smceq #0 @ encoding: [0x70,0x00,0x60,0x01] + diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 560a0d633cb..f73ae1449dd 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1790,15 +1790,6 @@ Lforward: @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6] @ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6] -@------------------------------------------------------------------------------ -@ SMC -@------------------------------------------------------------------------------ - smc #0xf - smceq #0 - -@ CHECK: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1] -@ CHECK: smceq #0 @ encoding: [0x70,0x00,0x60,0x01] - @------------------------------------------------------------------------------ @ SMLABB/SMLABT/SMLATB/SMLATT @------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt b/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt new file mode 100644 index 00000000000..d6b7cf1a0bb --- /dev/null +++ b/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + +#------------------------------------------------------------------------------ +# SMC +#------------------------------------------------------------------------------ + +0xff 0xf7 0x00 0x80 +0x0c 0xbf +0xf0 0xf7 0x00 0x80 + +# NOTZ-NOT: smc #15 +# NOTZ-NOT: smceq #0 +# TZ: smc #15 +# TZ: ite eq +# TZ: smceq #0 diff --git a/test/MC/Disassembler/ARM/arm-trustzone.txt b/test/MC/Disassembler/ARM/arm-trustzone.txt new file mode 100644 index 00000000000..92d5d6b2907 --- /dev/null +++ b/test/MC/Disassembler/ARM/arm-trustzone.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + +#------------------------------------------------------------------------------ +# SMC +#------------------------------------------------------------------------------ + +0x7f 0x00 0x60 0xe1 +0x70 0x00 0x60 0x01 + +# NOTZ-NOT: smc #15 +# NOTZ-NOT: smceq #0 +# TZ: smc #15 +# TZ: smceq #0 + diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 1100ce64a94..477ba728b39 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -1441,15 +1441,6 @@ 0xf2 0x4f 0x38 0xe6 0xf2 0x4f 0x38 0xc6 -#------------------------------------------------------------------------------ -# SMC -#------------------------------------------------------------------------------ -# CHECK: smc #15 -# CHECK: smceq #0 - -0x7f 0x00 0x60 0xe1 -0x70 0x00 0x60 0x01 - #------------------------------------------------------------------------------ # SMLABB/SMLABT/SMLATB/SMLATT #------------------------------------------------------------------------------ -- 2.34.1