From 8c0b3a0d31f2eb04d96f63b72e189fe82f8b4a4f Mon Sep 17 00:00:00 2001 From: Christian Konig Date: Thu, 21 Feb 2013 15:16:44 +0000 Subject: [PATCH] R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Those two files got mixed up. Signed-off-by: Christian König Reviewed-by: Tom Stellard Reviewed-by: Michel Dänzer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175746 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrFormats.td | 500 +++++++++++++++++++++-------- lib/Target/R600/SIInstrInfo.td | 515 +++++++++--------------------- 2 files changed, 527 insertions(+), 488 deletions(-) diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 40e37aa9260..fe417d6c60c 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -1,4 +1,4 @@ -//===-- SIInstrFormats.td - SI Instruction Formats ------------------------===// +//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// // // The LLVM Compiler Infrastructure // @@ -9,180 +9,418 @@ // // SI Instruction format definitions. // -// Instructions with _32 take 32-bit operands. -// Instructions with _64 take 64-bit operands. -// -// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit -// encoding is the standard encoding, but instruction that make use of -// any of the instruction modifiers must use the 64-bit encoding. -// -// Instructions with _e32 use the 32-bit encoding. -// Instructions with _e64 use the 64-bit encoding. -// //===----------------------------------------------------------------------===// -class VOP3_32 op, string opName, list pattern> - : VOP3 ; +class InstSI pattern> : + AMDGPUInst { + + field bits<1> VM_CNT = 0; + field bits<1> EXP_CNT = 0; + field bits<1> LGKM_CNT = 0; + + let TSFlags{0} = VM_CNT; + let TSFlags{1} = EXP_CNT; + let TSFlags{2} = LGKM_CNT; +} + +class Enc32 pattern> : + InstSI { + + field bits<32> Inst; + let Size = 4; +} -class VOP3_64 op, string opName, list pattern> - : VOP3 ; +class Enc64 pattern> : + InstSI { -class SOP1_32 op, string opName, list pattern> - : SOP1 ; + field bits<64> Inst; + let Size = 8; +} -class SOP1_64 op, string opName, list pattern> - : SOP1 ; +//===----------------------------------------------------------------------===// +// Scalar operations +//===----------------------------------------------------------------------===// -class SOP2_32 op, string opName, list pattern> - : SOP2 ; +class SOP1 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { -class SOP2_64 op, string opName, list pattern> - : SOP2 ; + bits<7> SDST; + bits<8> SSRC0; -class VOP1_Helper op, RegisterClass vrc, RegisterClass arc, - string opName, list pattern> : - VOP1 < - op, (outs vrc:$dst), (ins arc:$src0), opName, pattern - >; + let Inst{7-0} = SSRC0; + let Inst{15-8} = op; + let Inst{22-16} = SDST; + let Inst{31-23} = 0x17d; //encoding; -multiclass VOP1_32 op, string opName, list pattern> { - def _e32: VOP1_Helper ; - def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; } -multiclass VOP1_64 op, string opName, list pattern> { +class SOP2 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<7> SDST; + bits<8> SSRC0; + bits<8> SSRC1; - def _e32 : VOP1_Helper ; + let Inst{7-0} = SSRC0; + let Inst{15-8} = SSRC1; + let Inst{22-16} = SDST; + let Inst{29-23} = op; + let Inst{31-30} = 0x2; // encoding - def _e64 : VOP3_64 < - {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; } -class VOP2_Helper op, RegisterClass vrc, RegisterClass arc, - string opName, list pattern> : - VOP2 < - op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern - >; +class SOPC op, dag outs, dag ins, string asm, list pattern> : + Enc32 { -multiclass VOP2_32 op, string opName, list pattern> { + bits<8> SSRC0; + bits<8> SSRC1; - def _e32 : VOP2_Helper ; + let Inst{7-0} = SSRC0; + let Inst{15-8} = SSRC1; + let Inst{22-16} = op; + let Inst{31-23} = 0x17e; - def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; + let DisableEncoding = "$dst"; + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; } -multiclass VOP2_64 op, string opName, list pattern> { - def _e32: VOP2_Helper ; +class SOPK op, dag outs, dag ins, string asm, list pattern> : + Enc32 { - def _e64 : VOP3_64 < - {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; + bits <7> SDST; + bits <16> SIMM16; + + let Inst{15-0} = SIMM16; + let Inst{22-16} = SDST; + let Inst{27-23} = op; + let Inst{31-28} = 0xb; //encoding + + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; } -class SOPK_32 op, string opName, list pattern> - : SOPK ; +class SOPP op, dag ins, string asm, list pattern> : Enc32 < + (outs), + ins, + asm, + pattern > { -class SOPK_64 op, string opName, list pattern> - : SOPK ; + bits <16> SIMM16; -multiclass VOPC_Helper op, RegisterClass vrc, RegisterClass arc, - string opName, list pattern> { + let Inst{15-0} = SIMM16; + let Inst{22-16} = op; + let Inst{31-23} = 0x17f; // encoding - def _e32 : VOPC ; - def _e64 : VOP3 < - {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - (outs SReg_64:$dst), - (ins arc:$src0, vrc:$src1, - InstFlag:$abs, InstFlag:$clamp, - InstFlag:$omod, InstFlag:$neg), - opName, pattern - > { - let SRC2 = 0x80; - } + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; } -multiclass VOPC_32 op, string opName, list pattern> - : VOPC_Helper ; - -multiclass VOPC_64 op, string opName, list pattern> - : VOPC_Helper ; +class SMRD op, bits<1> imm, dag outs, dag ins, string asm, + list pattern> : Enc32 { + + bits<7> SDST; + bits<6> SBASE; + bits<8> OFFSET; + + let Inst{7-0} = OFFSET; + let Inst{8} = imm; + let Inst{14-9} = SBASE; + let Inst{21-15} = SDST; + let Inst{26-22} = op; + let Inst{31-27} = 0x18; //encoding + + let LGKM_CNT = 1; +} -class SOPC_32 op, string opName, list pattern> - : SOPC ; +//===----------------------------------------------------------------------===// +// Vector ALU operations +//===----------------------------------------------------------------------===// + +let Uses = [EXEC] in { + +class VOP1 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<8> VDST; + bits<9> SRC0; + + let Inst{8-0} = SRC0; + let Inst{16-9} = op; + let Inst{24-17} = VDST; + let Inst{31-25} = 0x3f; //encoding + + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; +} -class SOPC_64 op, string opName, list pattern> - : SOPC ; +class VOP2 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<8> VDST; + bits<9> SRC0; + bits<8> VSRC1; + + let Inst{8-0} = SRC0; + let Inst{16-9} = VSRC1; + let Inst{24-17} = VDST; + let Inst{30-25} = op; + let Inst{31} = 0x0; //encoding + + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; +} -class MIMG_Load_Helper op, string asm> : MIMG < - op, - (outs VReg_128:$vdata), - (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, - i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr, - GPR4Align:$srsrc, GPR4Align:$ssamp), - asm, - []> { - let mayLoad = 1; +class VOP3 op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDST; + bits<9> SRC0; + bits<9> SRC1; + bits<9> SRC2; + bits<3> ABS; + bits<1> CLAMP; + bits<2> OMOD; + bits<3> NEG; + + let Inst{7-0} = VDST; + let Inst{10-8} = ABS; + let Inst{11} = CLAMP; + let Inst{25-17} = op; + let Inst{31-26} = 0x34; //encoding + let Inst{40-32} = SRC0; + let Inst{49-41} = SRC1; + let Inst{58-50} = SRC2; + let Inst{60-59} = OMOD; + let Inst{63-61} = NEG; + + let mayLoad = 0; let mayStore = 0; + let hasSideEffects = 0; } -class MTBUF_Store_Helper op, string asm, RegisterClass regClass> : MTBUF < - op, - (outs), - (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, - i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, - GPR4Align:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset), - asm, - []> { - let mayStore = 1; +class VOP3b op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDST; + bits<9> SRC0; + bits<9> SRC1; + bits<9> SRC2; + bits<7> SDST; + bits<2> OMOD; + bits<3> NEG; + + let Inst{7-0} = VDST; + let Inst{14-8} = SDST; + let Inst{25-17} = op; + let Inst{31-26} = 0x34; //encoding + let Inst{40-32} = SRC0; + let Inst{49-41} = SRC1; + let Inst{58-50} = SRC2; + let Inst{60-59} = OMOD; + let Inst{63-61} = NEG; + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; } -class MUBUF_Load_Helper op, string asm, RegisterClass regClass> : MUBUF < - op, - (outs regClass:$dst), - (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, - i1imm:$lds, VReg_32:$vaddr, GPR4Align:$srsrc, i1imm:$slc, - i1imm:$tfe, SSrc_32:$soffset), - asm, - []> { - let mayLoad = 1; +class VOPC op, dag ins, string asm, list pattern> : + Enc32 <(outs VCCReg:$dst), ins, asm, pattern> { + + bits<9> SRC0; + bits<8> VSRC1; + + let Inst{8-0} = SRC0; + let Inst{16-9} = VSRC1; + let Inst{24-17} = op; + let Inst{31-25} = 0x3e; + + let DisableEncoding = "$dst"; + let mayLoad = 0; let mayStore = 0; + let hasSideEffects = 0; } -class MTBUF_Load_Helper op, string asm, RegisterClass regClass> : MTBUF < - op, - (outs regClass:$dst), - (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, - i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align:$srsrc, - i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset), - asm, - []> { +class VINTRP op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<8> VDST; + bits<8> VSRC; + bits<2> ATTRCHAN; + bits<6> ATTR; + + let Inst{7-0} = VSRC; + let Inst{9-8} = ATTRCHAN; + let Inst{15-10} = ATTR; + let Inst{17-16} = op; + let Inst{25-18} = VDST; + let Inst{31-26} = 0x32; // encoding + + let neverHasSideEffects = 1; let mayLoad = 1; let mayStore = 0; } -multiclass SMRD_Helper op, string asm, RegisterClass dstClass> { - def _IMM : SMRD < - op, 1, - (outs dstClass:$dst), - (ins GPR2Align:$sbase, i32imm:$offset), - asm, - [] - >; +} // End Uses = [EXEC] + +//===----------------------------------------------------------------------===// +// Vector I/O operations +//===----------------------------------------------------------------------===// - def _SGPR : SMRD < - op, 0, - (outs dstClass:$dst), - (ins GPR2Align:$sbase, SReg_32:$soff), - asm, - [] - >; +let Uses = [EXEC] in { + +class MUBUF op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDATA; + bits<12> OFFSET; + bits<1> OFFEN; + bits<1> IDXEN; + bits<1> GLC; + bits<1> ADDR64; + bits<1> LDS; + bits<8> VADDR; + bits<5> SRSRC; + bits<1> SLC; + bits<1> TFE; + bits<8> SOFFSET; + + let Inst{11-0} = OFFSET; + let Inst{12} = OFFEN; + let Inst{13} = IDXEN; + let Inst{14} = GLC; + let Inst{15} = ADDR64; + let Inst{16} = LDS; + let Inst{24-18} = op; + let Inst{31-26} = 0x38; //encoding + let Inst{39-32} = VADDR; + let Inst{47-40} = VDATA; + let Inst{52-48} = SRSRC; + let Inst{54} = SLC; + let Inst{55} = TFE; + let Inst{63-56} = SOFFSET; + + let VM_CNT = 1; + let EXP_CNT = 1; + + let neverHasSideEffects = 1; +} + +class MTBUF op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDATA; + bits<12> OFFSET; + bits<1> OFFEN; + bits<1> IDXEN; + bits<1> GLC; + bits<1> ADDR64; + bits<4> DFMT; + bits<3> NFMT; + bits<8> VADDR; + bits<5> SRSRC; + bits<1> SLC; + bits<1> TFE; + bits<8> SOFFSET; + + let Inst{11-0} = OFFSET; + let Inst{12} = OFFEN; + let Inst{13} = IDXEN; + let Inst{14} = GLC; + let Inst{15} = ADDR64; + let Inst{18-16} = op; + let Inst{22-19} = DFMT; + let Inst{25-23} = NFMT; + let Inst{31-26} = 0x3a; //encoding + let Inst{39-32} = VADDR; + let Inst{47-40} = VDATA; + let Inst{52-48} = SRSRC; + let Inst{54} = SLC; + let Inst{55} = TFE; + let Inst{63-56} = SOFFSET; + + let VM_CNT = 1; + let EXP_CNT = 1; + + let neverHasSideEffects = 1; +} + +class MIMG op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDATA; + bits<4> DMASK; + bits<1> UNORM; + bits<1> GLC; + bits<1> DA; + bits<1> R128; + bits<1> TFE; + bits<1> LWE; + bits<1> SLC; + bits<8> VADDR; + bits<5> SRSRC; + bits<5> SSAMP; + + let Inst{11-8} = DMASK; + let Inst{12} = UNORM; + let Inst{13} = GLC; + let Inst{14} = DA; + let Inst{15} = R128; + let Inst{16} = TFE; + let Inst{17} = LWE; + let Inst{24-18} = op; + let Inst{25} = SLC; + let Inst{31-26} = 0x3c; + let Inst{39-32} = VADDR; + let Inst{47-40} = VDATA; + let Inst{52-48} = SRSRC; + let Inst{57-53} = SSAMP; + + let VM_CNT = 1; + let EXP_CNT = 1; +} + +def EXP : Enc64< + (outs), + (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, + VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), + "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", + [] > { + + bits<4> EN; + bits<6> TGT; + bits<1> COMPR; + bits<1> DONE; + bits<1> VM; + bits<8> VSRC0; + bits<8> VSRC1; + bits<8> VSRC2; + bits<8> VSRC3; + + let Inst{3-0} = EN; + let Inst{9-4} = TGT; + let Inst{10} = COMPR; + let Inst{11} = DONE; + let Inst{12} = VM; + let Inst{31-26} = 0x3e; + let Inst{39-32} = VSRC0; + let Inst{47-40} = VSRC1; + let Inst{55-48} = VSRC2; + let Inst{63-56} = VSRC3; + + let EXP_CNT = 1; } +} // End Uses = [EXEC] diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 8c4e5afdeb7..cf0d5b936ae 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -1,4 +1,4 @@ -//===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===// +//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===// // // The LLVM Compiler Infrastructure // @@ -44,31 +44,10 @@ class InlineImm : ImmLeaf ; -class InstSI pattern> : - AMDGPUInst { - field bits<1> VM_CNT = 0; - field bits<1> EXP_CNT = 0; - field bits<1> LGKM_CNT = 0; - - let TSFlags{0} = VM_CNT; - let TSFlags{1} = EXP_CNT; - let TSFlags{2} = LGKM_CNT; -} - -class Enc32 pattern> : - InstSI { - - field bits<32> Inst; - let Size = 4; -} - -class Enc64 pattern> : - InstSI { - - field bits<64> Inst; - let Size = 8; -} +//===----------------------------------------------------------------------===// +// SI assembler operands +//===----------------------------------------------------------------------===// class SIOperand : Operand { let EncoderMethod = "encodeOperand"; @@ -85,381 +64,203 @@ class GPR2Align : Operand { let MIOperandInfo = (ops rc:$reg); } -let Uses = [EXEC] in { - -def EXP : Enc64< - (outs), - (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, - VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), - "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", - [] > { - - bits<4> EN; - bits<6> TGT; - bits<1> COMPR; - bits<1> DONE; - bits<1> VM; - bits<8> VSRC0; - bits<8> VSRC1; - bits<8> VSRC2; - bits<8> VSRC3; - - let Inst{3-0} = EN; - let Inst{9-4} = TGT; - let Inst{10} = COMPR; - let Inst{11} = DONE; - let Inst{12} = VM; - let Inst{31-26} = 0x3e; - let Inst{39-32} = VSRC0; - let Inst{47-40} = VSRC1; - let Inst{55-48} = VSRC2; - let Inst{63-56} = VSRC3; - - let EXP_CNT = 1; -} - -class MIMG op, dag outs, dag ins, string asm, list pattern> : - Enc64 { - - bits<8> VDATA; - bits<4> DMASK; - bits<1> UNORM; - bits<1> GLC; - bits<1> DA; - bits<1> R128; - bits<1> TFE; - bits<1> LWE; - bits<1> SLC; - bits<8> VADDR; - bits<5> SRSRC; - bits<5> SSAMP; - - let Inst{11-8} = DMASK; - let Inst{12} = UNORM; - let Inst{13} = GLC; - let Inst{14} = DA; - let Inst{15} = R128; - let Inst{16} = TFE; - let Inst{17} = LWE; - let Inst{24-18} = op; - let Inst{25} = SLC; - let Inst{31-26} = 0x3c; - let Inst{39-32} = VADDR; - let Inst{47-40} = VDATA; - let Inst{52-48} = SRSRC; - let Inst{57-53} = SSAMP; - - let VM_CNT = 1; - let EXP_CNT = 1; -} - -class MTBUF op, dag outs, dag ins, string asm, list pattern> : - Enc64 { - - bits<8> VDATA; - bits<12> OFFSET; - bits<1> OFFEN; - bits<1> IDXEN; - bits<1> GLC; - bits<1> ADDR64; - bits<4> DFMT; - bits<3> NFMT; - bits<8> VADDR; - bits<5> SRSRC; - bits<1> SLC; - bits<1> TFE; - bits<8> SOFFSET; - - let Inst{11-0} = OFFSET; - let Inst{12} = OFFEN; - let Inst{13} = IDXEN; - let Inst{14} = GLC; - let Inst{15} = ADDR64; - let Inst{18-16} = op; - let Inst{22-19} = DFMT; - let Inst{25-23} = NFMT; - let Inst{31-26} = 0x3a; //encoding - let Inst{39-32} = VADDR; - let Inst{47-40} = VDATA; - let Inst{52-48} = SRSRC; - let Inst{54} = SLC; - let Inst{55} = TFE; - let Inst{63-56} = SOFFSET; - - let VM_CNT = 1; - let EXP_CNT = 1; - - let neverHasSideEffects = 1; -} +include "SIInstrFormats.td" -class MUBUF op, dag outs, dag ins, string asm, list pattern> : - Enc64 { - - bits<8> VDATA; - bits<12> OFFSET; - bits<1> OFFEN; - bits<1> IDXEN; - bits<1> GLC; - bits<1> ADDR64; - bits<1> LDS; - bits<8> VADDR; - bits<5> SRSRC; - bits<1> SLC; - bits<1> TFE; - bits<8> SOFFSET; - - let Inst{11-0} = OFFSET; - let Inst{12} = OFFEN; - let Inst{13} = IDXEN; - let Inst{14} = GLC; - let Inst{15} = ADDR64; - let Inst{16} = LDS; - let Inst{24-18} = op; - let Inst{31-26} = 0x38; //encoding - let Inst{39-32} = VADDR; - let Inst{47-40} = VDATA; - let Inst{52-48} = SRSRC; - let Inst{54} = SLC; - let Inst{55} = TFE; - let Inst{63-56} = SOFFSET; - - let VM_CNT = 1; - let EXP_CNT = 1; - - let neverHasSideEffects = 1; -} +//===----------------------------------------------------------------------===// +// +// SI Instruction multiclass helpers. +// +// Instructions with _32 take 32-bit operands. +// Instructions with _64 take 64-bit operands. +// +// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit +// encoding is the standard encoding, but instruction that make use of +// any of the instruction modifiers must use the 64-bit encoding. +// +// Instructions with _e32 use the 32-bit encoding. +// Instructions with _e64 use the 64-bit encoding. +// +//===----------------------------------------------------------------------===// -} // End Uses = [EXEC] +//===----------------------------------------------------------------------===// +// Scalar classes +//===----------------------------------------------------------------------===// -class SMRD op, bits<1> imm, dag outs, dag ins, string asm, - list pattern> : Enc32 { +class SOP1_32 op, string opName, list pattern> + : SOP1 ; - bits<7> SDST; - bits<6> SBASE; - bits<8> OFFSET; - - let Inst{7-0} = OFFSET; - let Inst{8} = imm; - let Inst{14-9} = SBASE; - let Inst{21-15} = SDST; - let Inst{26-22} = op; - let Inst{31-27} = 0x18; //encoding +class SOP1_64 op, string opName, list pattern> + : SOP1 ; - let LGKM_CNT = 1; -} +class SOP2_32 op, string opName, list pattern> + : SOP2 ; -class SOP1 op, dag outs, dag ins, string asm, list pattern> : - Enc32 { +class SOP2_64 op, string opName, list pattern> + : SOP2 ; - bits<7> SDST; - bits<8> SSRC0; +class SOPC_32 op, string opName, list pattern> + : SOPC ; - let Inst{7-0} = SSRC0; - let Inst{15-8} = op; - let Inst{22-16} = SDST; - let Inst{31-23} = 0x17d; //encoding; +class SOPC_64 op, string opName, list pattern> + : SOPC ; - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; -} +class SOPK_32 op, string opName, list pattern> + : SOPK ; -class SOP2 op, dag outs, dag ins, string asm, list pattern> : - Enc32 { - - bits<7> SDST; - bits<8> SSRC0; - bits<8> SSRC1; +class SOPK_64 op, string opName, list pattern> + : SOPK ; - let Inst{7-0} = SSRC0; - let Inst{15-8} = SSRC1; - let Inst{22-16} = SDST; - let Inst{29-23} = op; - let Inst{31-30} = 0x2; // encoding +multiclass SMRD_Helper op, string asm, RegisterClass dstClass> { + def _IMM : SMRD < + op, 1, (outs dstClass:$dst), + (ins GPR2Align:$sbase, i32imm:$offset), + asm, [] + >; - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; + def _SGPR : SMRD < + op, 0, (outs dstClass:$dst), + (ins GPR2Align:$sbase, SReg_32:$soff), + asm, [] + >; } -class SOPC op, dag outs, dag ins, string asm, list pattern> : - Enc32 { +//===----------------------------------------------------------------------===// +// Vector ALU classes +//===----------------------------------------------------------------------===// - bits<8> SSRC0; - bits<8> SSRC1; +class VOP3_32 op, string opName, list pattern> : VOP3 < + op, (outs VReg_32:$dst), + (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, + i32imm:$src4, i32imm:$src5, i32imm:$src6), + opName, pattern +>; - let Inst{7-0} = SSRC0; - let Inst{15-8} = SSRC1; - let Inst{22-16} = op; - let Inst{31-23} = 0x17e; +class VOP3_64 op, string opName, list pattern> : VOP3 < + op, (outs VReg_64:$dst), + (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2, + i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), + opName, pattern +>; - let DisableEncoding = "$dst"; - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; +class VOP1_Helper op, RegisterClass vrc, RegisterClass arc, + string opName, list pattern> : + VOP1 < + op, (outs vrc:$dst), (ins arc:$src0), opName, pattern + >; + +multiclass VOP1_32 op, string opName, list pattern> { + def _e32: VOP1_Helper ; + def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; } -class SOPK op, dag outs, dag ins, string asm, list pattern> : - Enc32 { +multiclass VOP1_64 op, string opName, list pattern> { - bits <7> SDST; - bits <16> SIMM16; - - let Inst{15-0} = SIMM16; - let Inst{22-16} = SDST; - let Inst{27-23} = op; - let Inst{31-28} = 0xb; //encoding + def _e32 : VOP1_Helper ; - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; + def _e64 : VOP3_64 < + {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; } -class SOPP op, dag ins, string asm, list pattern> : Enc32 < - (outs), - ins, - asm, - pattern > { +class VOP2_Helper op, RegisterClass vrc, RegisterClass arc, + string opName, list pattern> : + VOP2 < + op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern + >; - bits <16> SIMM16; +multiclass VOP2_32 op, string opName, list pattern> { - let Inst{15-0} = SIMM16; - let Inst{22-16} = op; - let Inst{31-23} = 0x17f; // encoding + def _e32 : VOP2_Helper ; - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; + def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; } - -let Uses = [EXEC] in { - -class VINTRP op, dag outs, dag ins, string asm, list pattern> : - Enc32 { - bits<8> VDST; - bits<8> VSRC; - bits<2> ATTRCHAN; - bits<6> ATTR; +multiclass VOP2_64 op, string opName, list pattern> { + def _e32: VOP2_Helper ; - let Inst{7-0} = VSRC; - let Inst{9-8} = ATTRCHAN; - let Inst{15-10} = ATTR; - let Inst{17-16} = op; - let Inst{25-18} = VDST; - let Inst{31-26} = 0x32; // encoding - - let neverHasSideEffects = 1; - let mayLoad = 1; - let mayStore = 0; + def _e64 : VOP3_64 < + {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; } -class VOP1 op, dag outs, dag ins, string asm, list pattern> : - Enc32 { - - bits<8> VDST; - bits<9> SRC0; - - let Inst{8-0} = SRC0; - let Inst{16-9} = op; - let Inst{24-17} = VDST; - let Inst{31-25} = 0x3f; //encoding - - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; +multiclass VOPC_Helper op, RegisterClass vrc, RegisterClass arc, + string opName, list pattern> { + + def _e32 : VOPC ; + def _e64 : VOP3 < + {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + (outs SReg_64:$dst), + (ins arc:$src0, vrc:$src1, + InstFlag:$abs, InstFlag:$clamp, + InstFlag:$omod, InstFlag:$neg), + opName, pattern + > { + let SRC2 = 0x80; + } } -class VOP2 op, dag outs, dag ins, string asm, list pattern> : - Enc32 { - - bits<8> VDST; - bits<9> SRC0; - bits<8> VSRC1; - - let Inst{8-0} = SRC0; - let Inst{16-9} = VSRC1; - let Inst{24-17} = VDST; - let Inst{30-25} = op; - let Inst{31} = 0x0; //encoding - +multiclass VOPC_32 op, string opName, list pattern> + : VOPC_Helper ; + +multiclass VOPC_64 op, string opName, list pattern> + : VOPC_Helper ; + +//===----------------------------------------------------------------------===// +// Vector I/O classes +//===----------------------------------------------------------------------===// + +class MTBUF_Store_Helper op, string asm, RegisterClass regClass> : MTBUF < + op, + (outs), + (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, + i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, + GPR4Align:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset), + asm, + []> { + let mayStore = 1; let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; } -class VOP3 op, dag outs, dag ins, string asm, list pattern> : - Enc64 { - - bits<8> VDST; - bits<9> SRC0; - bits<9> SRC1; - bits<9> SRC2; - bits<3> ABS; - bits<1> CLAMP; - bits<2> OMOD; - bits<3> NEG; - - let Inst{7-0} = VDST; - let Inst{10-8} = ABS; - let Inst{11} = CLAMP; - let Inst{25-17} = op; - let Inst{31-26} = 0x34; //encoding - let Inst{40-32} = SRC0; - let Inst{49-41} = SRC1; - let Inst{58-50} = SRC2; - let Inst{60-59} = OMOD; - let Inst{63-61} = NEG; - - let mayLoad = 0; +class MUBUF_Load_Helper op, string asm, RegisterClass regClass> : MUBUF < + op, + (outs regClass:$dst), + (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, + i1imm:$lds, VReg_32:$vaddr, GPR4Align:$srsrc, i1imm:$slc, + i1imm:$tfe, SSrc_32:$soffset), + asm, + []> { + let mayLoad = 1; let mayStore = 0; - let hasSideEffects = 0; } -class VOP3b op, dag outs, dag ins, string asm, list pattern> : - Enc64 { - - bits<8> VDST; - bits<9> SRC0; - bits<9> SRC1; - bits<9> SRC2; - bits<7> SDST; - bits<2> OMOD; - bits<3> NEG; - - let Inst{7-0} = VDST; - let Inst{14-8} = SDST; - let Inst{25-17} = op; - let Inst{31-26} = 0x34; //encoding - let Inst{40-32} = SRC0; - let Inst{49-41} = SRC1; - let Inst{58-50} = SRC2; - let Inst{60-59} = OMOD; - let Inst{63-61} = NEG; - - let mayLoad = 0; +class MTBUF_Load_Helper op, string asm, RegisterClass regClass> : MTBUF < + op, + (outs regClass:$dst), + (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, + i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align:$srsrc, + i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset), + asm, + []> { + let mayLoad = 1; let mayStore = 0; - let hasSideEffects = 0; } -class VOPC op, dag ins, string asm, list pattern> : - Enc32 <(outs VCCReg:$dst), ins, asm, pattern> { - - bits<9> SRC0; - bits<8> VSRC1; - - let Inst{8-0} = SRC0; - let Inst{16-9} = VSRC1; - let Inst{24-17} = op; - let Inst{31-25} = 0x3e; - - let DisableEncoding = "$dst"; - let mayLoad = 0; +class MIMG_Load_Helper op, string asm> : MIMG < + op, + (outs VReg_128:$vdata), + (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, + i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr, + GPR4Align:$srsrc, GPR4Align:$ssamp), + asm, + []> { + let mayLoad = 1; let mayStore = 0; - let hasSideEffects = 0; } -} // End Uses = [EXEC] - -include "SIInstrFormats.td" include "SIInstructions.td" -- 2.34.1