From 89ba74d117577f5a1bd62ee209dc2ecb090172e3 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 22 Jul 2010 06:24:48 +0000
Subject: [PATCH] Re-apply r109079 with fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109083 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../SelectionDAG/ScheduleDAGRRList.cpp        | 54 +++++++++----------
 1 file changed, 26 insertions(+), 28 deletions(-)

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 6e822499282..334ce58ac7c 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1036,7 +1036,7 @@ namespace {
     std::vector<SUnit*> Queue;
     SF Picker;
     unsigned CurQueueId;
-    bool isBottomUp;
+    bool TracksRegPressure;
 
   protected:
     // SUnits - The SUnits for the current graph.
@@ -1061,20 +1061,22 @@ namespace {
 
   public:
     RegReductionPriorityQueue(MachineFunction &mf,
-                              bool isbottomup,
+                              bool tracksrp,
                               const TargetInstrInfo *tii,
                               const TargetRegisterInfo *tri,
                               const TargetLowering *tli)
-      : Picker(this), CurQueueId(0), isBottomUp(isbottomup),
+      : Picker(this), CurQueueId(0), TracksRegPressure(tracksrp),
         MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
-      unsigned NumRC = TRI->getNumRegClasses();
-      RegLimit.resize(NumRC);
-      RegPressure.resize(NumRC);
-      std::fill(RegLimit.begin(), RegLimit.end(), 0);
-      std::fill(RegPressure.begin(), RegPressure.end(), 0);
-      for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
-             E = TRI->regclass_end(); I != E; ++I)
-        RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
+      if (TracksRegPressure) {
+        unsigned NumRC = TRI->getNumRegClasses();
+        RegLimit.resize(NumRC);
+        RegPressure.resize(NumRC);
+        std::fill(RegLimit.begin(), RegLimit.end(), 0);
+        std::fill(RegPressure.begin(), RegPressure.end(), 0);
+        for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
+               E = TRI->regclass_end(); I != E; ++I)
+          RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
+      }
     }
     
     void initNodes(std::vector<SUnit> &sunits) {
@@ -1207,7 +1209,10 @@ namespace {
       return false;
     }
 
-    void OpenPredLives(SUnit *SU) {
+    void ScheduledNode(SUnit *SU) {
+      if (!TracksRegPressure)
+        return;
+
       const SDNode *N = SU->getNode();
       if (!N->isMachineOpcode())
         return;
@@ -1260,9 +1265,14 @@ namespace {
         else
           RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
       }
+
+      dumpRegPressure();
     }
 
-    void ClosePredLives(SUnit *SU) {
+    void UnscheduledNode(SUnit *SU) {
+      if (!TracksRegPressure)
+        return;
+
       const SDNode *N = SU->getNode();
       if (!N->isMachineOpcode())
         return;
@@ -1317,19 +1327,7 @@ namespace {
         unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
         RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
       }
-    }
 
-    void ScheduledNode(SUnit *SU) {
-      if (!TLI || !isBottomUp)
-        return;
-      OpenPredLives(SU);
-      dumpRegPressure();
-    }
-
-    void UnscheduledNode(SUnit *SU) {
-      if (!TLI || !isBottomUp)
-        return;
-      ClosePredLives(SU);
       dumpRegPressure();
     }
 
@@ -1851,7 +1849,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
   
   BURegReductionPriorityQueue *PQ =
-    new BURegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
+    new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
   ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
   PQ->setScheduleDAG(SD);
   return SD;  
@@ -1877,7 +1875,7 @@ llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
   
   SrcRegReductionPriorityQueue *PQ =
-    new SrcRegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
+    new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
   ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
   PQ->setScheduleDAG(SD);
   return SD;  
@@ -1891,7 +1889,7 @@ llvm::createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   const TargetLowering *TLI = &IS->getTargetLowering();
   
   HybridBURRPriorityQueue *PQ =
-    new HybridBURRPriorityQueue(*IS->MF, true, TII, TRI,
+    new HybridBURRPriorityQueue(*IS->MF, RegPressureAware, TII, TRI,
                                 (RegPressureAware ? TLI : 0));
   ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, true, PQ);
   PQ->setScheduleDAG(SD);
-- 
2.34.1