From 8557c2bcb8002169d890eb8485e9a1d7219e4343 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 19 Jun 2009 01:51:50 +0000 Subject: [PATCH] Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARM.td | 94 ++++++++++++++++------------- lib/Target/ARM/ARMISelLowering.cpp | 15 +++++ lib/Target/ARM/ARMInstrInfo.td | 4 +- lib/Target/ARM/ARMSchedule.td | 35 +++++++++++ lib/Target/ARM/ARMScheduleV6.td | 22 +++++++ lib/Target/ARM/ARMSubtarget.h | 8 +++ lib/Target/ARM/ARMTargetMachine.cpp | 3 +- lib/Target/ARM/ARMTargetMachine.h | 18 +++--- 8 files changed, 147 insertions(+), 52 deletions(-) create mode 100644 lib/Target/ARM/ARMSchedule.td create mode 100644 lib/Target/ARM/ARMScheduleV6.td diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 594811d6357..9001e5033c7 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -45,62 +45,72 @@ def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", // ARM Processors supported. // -class Proc Features> - : Processor; +include "ARMSchedule.td" + +class ProcNoItin Features> + : Processor; // V4 Processors. -def : Proc<"generic", []>; -def : Proc<"arm8", []>; -def : Proc<"arm810", []>; -def : Proc<"strongarm", []>; -def : Proc<"strongarm110", []>; -def : Proc<"strongarm1100", []>; -def : Proc<"strongarm1110", []>; +def : ProcNoItin<"generic", []>; +def : ProcNoItin<"arm8", []>; +def : ProcNoItin<"arm810", []>; +def : ProcNoItin<"strongarm", []>; +def : ProcNoItin<"strongarm110", []>; +def : ProcNoItin<"strongarm1100", []>; +def : ProcNoItin<"strongarm1110", []>; // V4T Processors. -def : Proc<"arm7tdmi", [ArchV4T]>; -def : Proc<"arm7tdmi-s", [ArchV4T]>; -def : Proc<"arm710t", [ArchV4T]>; -def : Proc<"arm720t", [ArchV4T]>; -def : Proc<"arm9", [ArchV4T]>; -def : Proc<"arm9tdmi", [ArchV4T]>; -def : Proc<"arm920", [ArchV4T]>; -def : Proc<"arm920t", [ArchV4T]>; -def : Proc<"arm922t", [ArchV4T]>; -def : Proc<"arm940t", [ArchV4T]>; -def : Proc<"ep9312", [ArchV4T]>; +def : ProcNoItin<"arm7tdmi", [ArchV4T]>; +def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; +def : ProcNoItin<"arm710t", [ArchV4T]>; +def : ProcNoItin<"arm720t", [ArchV4T]>; +def : ProcNoItin<"arm9", [ArchV4T]>; +def : ProcNoItin<"arm9tdmi", [ArchV4T]>; +def : ProcNoItin<"arm920", [ArchV4T]>; +def : ProcNoItin<"arm920t", [ArchV4T]>; +def : ProcNoItin<"arm922t", [ArchV4T]>; +def : ProcNoItin<"arm940t", [ArchV4T]>; +def : ProcNoItin<"ep9312", [ArchV4T]>; // V5T Processors. -def : Proc<"arm10tdmi", [ArchV5T]>; -def : Proc<"arm1020t", [ArchV5T]>; +def : ProcNoItin<"arm10tdmi", [ArchV5T]>; +def : ProcNoItin<"arm1020t", [ArchV5T]>; // V5TE Processors. -def : Proc<"arm9e", [ArchV5TE]>; -def : Proc<"arm926ej-s", [ArchV5TE]>; -def : Proc<"arm946e-s", [ArchV5TE]>; -def : Proc<"arm966e-s", [ArchV5TE]>; -def : Proc<"arm968e-s", [ArchV5TE]>; -def : Proc<"arm10e", [ArchV5TE]>; -def : Proc<"arm1020e", [ArchV5TE]>; -def : Proc<"arm1022e", [ArchV5TE]>; -def : Proc<"xscale", [ArchV5TE]>; -def : Proc<"iwmmxt", [ArchV5TE]>; +def : ProcNoItin<"arm9e", [ArchV5TE]>; +def : ProcNoItin<"arm926ej-s", [ArchV5TE]>; +def : ProcNoItin<"arm946e-s", [ArchV5TE]>; +def : ProcNoItin<"arm966e-s", [ArchV5TE]>; +def : ProcNoItin<"arm968e-s", [ArchV5TE]>; +def : ProcNoItin<"arm10e", [ArchV5TE]>; +def : ProcNoItin<"arm1020e", [ArchV5TE]>; +def : ProcNoItin<"arm1022e", [ArchV5TE]>; +def : ProcNoItin<"xscale", [ArchV5TE]>; +def : ProcNoItin<"iwmmxt", [ArchV5TE]>; // V6 Processors. -def : Proc<"arm1136j-s", [ArchV6]>; -def : Proc<"arm1136jf-s", [ArchV6, FeatureVFP2]>; -def : Proc<"arm1176jz-s", [ArchV6]>; -def : Proc<"arm1176jzf-s", [ArchV6, FeatureVFP2]>; -def : Proc<"mpcorenovfp", [ArchV6]>; -def : Proc<"mpcore", [ArchV6, FeatureVFP2]>; +def : Processor<"arm1136j-s", V6Itineraries, + [ArchV6]>; +def : Processor<"arm1136jf-s", V6Itineraries, + [ArchV6, FeatureVFP2]>; +def : Processor<"arm1176jz-s", V6Itineraries, + [ArchV6]>; +def : Processor<"arm1176jzf-s", V6Itineraries, + [ArchV6, FeatureVFP2]>; +def : Processor<"mpcorenovfp", V6Itineraries, + [ArchV6]>; +def : Processor<"mpcore", V6Itineraries, + [ArchV6, FeatureVFP2]>; // V6T2 Processors. -def : Proc<"arm1156t2-s", [ArchV6T2, FeatureThumb2]>; -def : Proc<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>; +def : Processor<"arm1156t2-s", V6Itineraries, + [ArchV6T2, FeatureThumb2]>; +def : Processor<"arm1156t2f-s", V6Itineraries, + [ArchV6T2, FeatureThumb2, FeatureVFP2]>; // V7 Processors. -def : Proc<"cortex-a8", [ArchV7A, FeatureThumb2, FeatureNEON]>; -def : Proc<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; +def : ProcNoItin<"cortex-a8", [ArchV7A, FeatureThumb2, FeatureNEON]>; +def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 943a4203c19..38a2fb9b4d0 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -292,6 +292,21 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); + if (!Subtarget->isThumb()) { + // Use branch latency information to determine if-conversion limits. + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData(); + unsigned Latency = InstrItins.getLatency(TII->get(ARM::BL).getSchedClass()); + if (Latency > 1) { + setIfCvtBlockSizeLimit(Latency-1); + if (Latency > 2) + setIfCvtDupBlockSizeLimit(Latency-2); + } else { + setIfCvtBlockSizeLimit(10); + setIfCvtDupBlockSizeLimit(2); + } + } + maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type // Do not enable CodePlacementOpt for now: it currently runs after the // ARMConstantIslandPass and messes up branch relaxation and placement diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 5c0bd97fa9f..4707e3b7a97 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -539,7 +539,7 @@ let isReturn = 1, isTerminator = 1 in LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", []>; -let isCall = 1, +let isCall = 1, Itinerary = IIC_Br, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), @@ -567,7 +567,7 @@ let isCall = 1, } } -let isBranch = 1, isTerminator = 1 in { +let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in { // B is "predicable" since it can be xformed into a Bcc. let isBarrier = 1 in { let isPredicable = 1 in diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td new file mode 100644 index 00000000000..75fa707f9f9 --- /dev/null +++ b/lib/Target/ARM/ARMSchedule.td @@ -0,0 +1,35 @@ +//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Functional units across ARM processors +// +def FU_iALU : FuncUnit; // Integer alu unit +def FU_iLdSt : FuncUnit; // Integer load / store unit +def FU_FpALU : FuncUnit; // FP alu unit +def FU_FpLdSt : FuncUnit; // FP load / store unit +def FU_Br : FuncUnit; // Branch unit + +//===----------------------------------------------------------------------===// +// Instruction Itinerary classes used for ARM +// +def IIC_iALU : InstrItinClass; +def IIC_iLoad : InstrItinClass; +def IIC_iStore : InstrItinClass; +def IIC_fpALU : InstrItinClass; +def IIC_fpLoad : InstrItinClass; +def IIC_fpStore : InstrItinClass; +def IIC_Br : InstrItinClass; + +//===----------------------------------------------------------------------===// +// Processor instruction itineraries. + +def GenericItineraries : ProcessorItineraries<[]>; + +include "ARMScheduleV6.td" diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td new file mode 100644 index 00000000000..596a57f8aef --- /dev/null +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -0,0 +1,22 @@ +//===- ARMSchedule.td - ARM v6 Scheduling Definitions ------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the itinerary class data for the ARM v6 processors. +// +//===----------------------------------------------------------------------===// + +def V6Itineraries : ProcessorItineraries<[ + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]> +]>; diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index c365750d071..c3cc7fff6e3 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -14,6 +14,7 @@ #ifndef ARMSUBTARGET_H #define ARMSUBTARGET_H +#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetSubtarget.h" #include @@ -58,6 +59,9 @@ protected: /// CPUString - String name of used CPU. std::string CPUString; + /// Selected instruction itineraries (one entry per itinerary class.) + InstrItineraryData InstrItins; + public: enum { isELF, isDarwin @@ -110,6 +114,10 @@ protected: const std::string & getCPUString() const { return CPUString; } + /// getInstrItins - Return the instruction itineraies based on subtarget + /// selection. + const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } + /// getStackAlignment - Returns the minimum alignment known to hold of the /// stack frame on entry to the function and which must be maintained by every /// function for this subtarget. diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 04dcd93a344..dec023231e1 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -102,7 +102,8 @@ ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS, InstrInfo(Subtarget), FrameInfo(Subtarget), JITInfo(), - TLInfo(*this) { + TLInfo(*this), + InstrItins(Subtarget.getInstrItineraryData()) { DefRelocModel = getRelocationModel(); } diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index 7192c1bb618..c4c8e6c1d98 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -28,13 +28,14 @@ namespace llvm { class Module; class ARMTargetMachine : public LLVMTargetMachine { - ARMSubtarget Subtarget; - const TargetData DataLayout; // Calculates type size & alignment - ARMInstrInfo InstrInfo; - ARMFrameInfo FrameInfo; - ARMJITInfo JITInfo; - ARMTargetLowering TLInfo; - Reloc::Model DefRelocModel; // Reloc model before it's overridden. + ARMSubtarget Subtarget; + const TargetData DataLayout; // Calculates type size & alignment + ARMInstrInfo InstrInfo; + ARMFrameInfo FrameInfo; + ARMJITInfo JITInfo; + ARMTargetLowering TLInfo; + InstrItineraryData InstrItins; + Reloc::Model DefRelocModel; // Reloc model before it's overridden. protected: // To avoid having target depend on the asmprinter stuff libraries, asmprinter @@ -59,6 +60,9 @@ public: virtual ARMTargetLowering *getTargetLowering() const { return const_cast(&TLInfo); } + virtual const InstrItineraryData getInstrItineraryData() const { + return InstrItins; + } static void registerAsmPrinter(AsmPrinterCtorFn F) { AsmPrinterCtor = F; -- 2.34.1