From 848278638c373a12e6dd9c281e97b4d2cfc179ed Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Mon, 2 Feb 2015 22:11:36 +0000 Subject: [PATCH] Cache and use the subtarget that owns the target lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227871 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonISelLowering.cpp | 36 +++++++++------------- lib/Target/Hexagon/HexagonISelLowering.h | 7 +++-- lib/Target/Hexagon/HexagonSubtarget.cpp | 2 +- 3 files changed, 20 insertions(+), 25 deletions(-) diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index daf56604709..b0f78a3a789 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -463,8 +463,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVector, 16> RegsToPass; SmallVector MemOpChains; - const HexagonRegisterInfo *QRI = static_cast( - DAG.getSubtarget().getRegisterInfo()); + const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo(); SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy()); @@ -722,9 +721,7 @@ SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, cast(Node->getOperand(i))->getReg(); // Check it to be lr - const HexagonRegisterInfo *QRI = - static_cast( - DAG.getSubtarget().getRegisterInfo()); + const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo(); if (Reg == QRI->getRARegister()) { FuncInfo->setHasClobberLR(true); break; @@ -817,8 +814,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, // The Sub result contains the new stack start address, so it // must be placed in the stack pointer register. - const HexagonRegisterInfo *QRI = static_cast( - DAG.getSubtarget().getRegisterInfo()); + const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo(); SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub); SDValue Ops[2] = { ArgAdjust, CopyChain }; @@ -965,7 +961,7 @@ HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { SDValue HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { - const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MFI->setReturnAddressIsTaken(true); @@ -991,8 +987,7 @@ HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { SDValue HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { - const HexagonRegisterInfo *TRI = static_cast( - DAG.getSubtarget().getRegisterInfo()); + const HexagonRegisterInfo *TRI = Subtarget->getRegisterInfo(); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setFrameAddressIsTaken(true); @@ -1044,17 +1039,15 @@ HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { // TargetLowering Implementation //===----------------------------------------------------------------------===// -HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) - : TargetLowering(targetmachine), - TM(targetmachine) { - - const HexagonSubtarget &Subtarget = TM.getSubtarget(); +HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, + const HexagonSubtarget &STI) + : TargetLowering(TM), Subtarget(&STI) { // Set up the register classes. addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); - if (Subtarget.hasV5TOps()) { + if (Subtarget->hasV5TOps()) { addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); } @@ -1120,7 +1113,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) setOperationAction(ISD::FSIN, MVT::f32, Expand); setOperationAction(ISD::FSIN, MVT::f64, Expand); - if (Subtarget.hasV5TOps()) { + if (Subtarget->hasV5TOps()) { // Hexagon V5 Support. setOperationAction(ISD::FADD, MVT::f32, Legal); setOperationAction(ISD::FADD, MVT::f64, Expand); @@ -1346,7 +1339,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); - if (Subtarget.hasV5TOps()) { + if (Subtarget->hasV5TOps()) { // We need to make the operation type of SELECT node to be Custom, // such that we don't go into the infinite loop of @@ -1441,7 +1434,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); - if (Subtarget.isSubtargetV2()) { + if (Subtarget->isSubtargetV2()) { setExceptionPointerRegister(Hexagon::R20); setExceptionSelectorRegister(Hexagon::R21); } else { @@ -1465,8 +1458,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) setMinFunctionAlignment(2); // Needed for DYNAMIC_STACKALLOC expansion. - const HexagonRegisterInfo *QRI = static_cast( - TM.getSubtargetImpl()->getRegisterInfo()); + const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo(); setStackPointerRegisterToSaveRestore(QRI->getStackRegister()); setSchedulingPreference(Sched::VLIW); } @@ -1637,7 +1629,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const /// specified FP immediate natively. If false, the legalizer will /// materialize the FP immediate as a load from a constant pool. bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { - return TM.getSubtarget().hasV5TOps(); + return Subtarget->hasV5TOps(); } /// isLegalAddressingMode - Return true if the addressing mode represented by diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 822a191766b..0c52c3dd2e2 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -77,6 +77,8 @@ bool isPositiveHalfWord(SDNode *N); }; } + class HexagonSubtarget; + class HexagonTargetLowering : public TargetLowering { int VarArgsFrameOffset; // Frame offset to start of varargs area. @@ -84,8 +86,9 @@ bool isPositiveHalfWord(SDNode *N); unsigned& RetSize) const; public: - const TargetMachine &TM; - explicit HexagonTargetLowering(const TargetMachine &targetmachine); + const HexagonSubtarget *Subtarget; + explicit HexagonTargetLowering(const TargetMachine &TM, + const HexagonSubtarget &Subtarget); /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Targets which want to do tail call diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index 19c9ecd1cef..acf7e67d8e0 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -74,7 +74,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, const TargetMachine &TM) : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()), - InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM), + InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() { // Initialize scheduling itinerary for the specified CPU. -- 2.34.1