From 8359916759a53e51f36e2e450db0b3ed10fb0664 Mon Sep 17 00:00:00 2001 From: Jozef Kolek Date: Thu, 7 May 2015 17:12:23 +0000 Subject: [PATCH] [mips][microMIPSr6] Implement JIALC and JIC instructions This patch implements JIALC and JIC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8389 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236748 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrInfo.td | 26 +++++++++++++++++++++ lib/Target/Mips/Mips32r6InstrInfo.td | 7 +++--- test/MC/Disassembler/Mips/micromips32r6.txt | 4 ++++ test/MC/Mips/micromips32r6/valid.s | 2 ++ 4 files changed, 36 insertions(+), 3 deletions(-) diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 59cf3e79d13..209d877b240 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -23,6 +23,8 @@ class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>; +class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>; +class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>; class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>; class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>; class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>; @@ -83,6 +85,28 @@ class CACHE_HINT_MMR6_DESC; class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>; +class JMP_MMR6_IDX_COMPACT_DESC_BASE + : MMR6Arch { + dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); + string AsmString = !strconcat(opstr, "\t$rt, $offset"); + list Pattern = []; + bit isTerminator = 1; + bit hasDelaySlot = 0; +} + +class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, + GPR32Opnd> { + bit isCall = 1; + list Defs = [RA]; +} + +class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, + GPR32Opnd> { + bit isBarrier = 1; + list Defs = [AT]; +} + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -98,6 +122,8 @@ def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC, ISA_MICROMIPS32R6; def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6; +def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6; +def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6; def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6; def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6; def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6; diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 485a3e13972..2d7ea8974e7 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -374,7 +374,8 @@ class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>; class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>; class JMP_IDX_COMPACT_DESC_BASE { + RegisterOperand GPROpnd> + : MipsR6Arch { dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); string AsmString = !strconcat(opstr, "\t$rt, $offset"); list Pattern = []; @@ -686,8 +687,8 @@ defm S : CMP_CC_M; defm D : CMP_CC_M; def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; -def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; -def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6; +def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; +def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index 6e2990ccbcb..8ea4ca0dcaa 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -18,6 +18,10 @@ # CHECK: cache 1, 8($5) 0x20 0x25 0x60 0x08 +0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256 + +0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256 + 0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5 0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5 diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 253f08e2201..22fb0048365 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -8,6 +8,8 @@ bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] + jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00] + jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] -- 2.34.1