From 7ef5520e8c349ecb927958fbab6fd038ba253be7 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Mon, 16 Dec 2013 17:15:29 +0000 Subject: [PATCH] On DataLayout, omit the default of p:64:64:64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197397 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +- lib/Target/Mips/MipsTargetMachine.cpp | 6 ++---- lib/Target/NVPTX/NVPTXTargetMachine.cpp | 4 +--- lib/Target/PowerPC/PPCTargetMachine.cpp | 6 ++---- lib/Target/R600/AMDGPUTargetMachine.cpp | 4 +--- lib/Target/Sparc/SparcTargetMachine.cpp | 6 ++---- lib/Target/SystemZ/SystemZTargetMachine.cpp | 2 +- lib/Target/X86/X86TargetMachine.cpp | 4 +--- 8 files changed, 11 insertions(+), 23 deletions(-) diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index ea80af48d3e..bfa496075b6 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -34,7 +34,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), Subtarget(TT, CPU, FS), InstrInfo(Subtarget), - DL("e-p:64:64-i64:64:64-i128:128:128-s:32:32-n32:64-S128"), + DL("e-i64:64:64-i128:128:128-s:32:32-n32:64-S128"), TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget) { diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index e476488071b..30762c6a729 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -54,10 +54,8 @@ static std::string computeDataLayout(const MipsSubtarget &ST) { else Ret += "E"; - // Pointers are 64 or 32 bit depending on the ABI. - if (ST.isABI_N64()) - Ret += "-p:64:64:64"; - else + // Pointers are 32 bit on some ABIs. + if (!ST.isABI_N64()) Ret += "-p:32:32:32"; // 8 and 16 bit integers only need no have natural alignment, but try to diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/lib/Target/NVPTX/NVPTXTargetMachine.cpp index d2735a63bd5..272940d4dc6 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -66,9 +66,7 @@ extern "C" void LLVMInitializeNVPTXTarget() { static std::string computeDataLayout(const NVPTXSubtarget &ST) { std::string Ret = "e"; - if (ST.is64Bit()) - Ret += "-p:64:64:64"; - else + if (!ST.is64Bit()) Ret += "-p:32:32:32"; Ret += "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 561b5e60bee..25badb1d0b6 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -38,10 +38,8 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) { // PPC is big endian. std::string Ret = "E"; - // PPC64 has 64 bit pointers, PPC32 has 32 bit pointers. - if (ST.isPPC64()) - Ret += "-p:64:64"; - else + // PPC32 has 32 bit pointers. + if (!ST.isPPC64()) Ret += "-p:32:32"; // Note, the alignment values for f64 and i64 on ppc64 in Darwin diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 762a17ae071..ae56e7923df 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -61,9 +61,7 @@ static std::string computeDataLayout(const AMDGPUSubtarget &ST) { if (ST.hasHWFP64()) DataLayout.append("-f64:64:64"); - if (ST.is64bit()) - DataLayout.append("-p:64:64:64"); - else + if (!ST.is64bit()) DataLayout.append("-p:32:32:32"); if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 36d2f6f778d..7324e99af91 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -27,10 +27,8 @@ static std::string computeDataLayout(const SparcSubtarget &ST) { // Sparc is big endian. std::string Ret = "E"; - // V9 has 64 bit pointers, others have 32bit pointers. - if (ST.is64Bit()) - Ret += "-p:64:64:64"; - else + // Some ABIs have 32bit pointers. + if (!ST.is64Bit()) Ret += "-p:32:32:32"; // Alignments for 64 bit integers. diff --git a/lib/Target/SystemZ/SystemZTargetMachine.cpp b/lib/Target/SystemZ/SystemZTargetMachine.cpp index fd947ee9faa..132608961a6 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -30,7 +30,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT, // Make sure that global data has at least 16 bits of alignment by default, // so that we can refer to it using LARL. We don't have any special // requirements for stack variables though. - DL("E-p:64:64:64-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"), + DL("E-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(*this, Subtarget) { initAsmInfo(); diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 274808839cd..4675a4ec03d 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -34,11 +34,9 @@ static std::string computeDataLayout(const X86Subtarget &ST) { // X86 is little endian std::string Ret = "e"; - // X86 and x32 have 32 bit pointers, x86-64 has 64 bit pointers + // X86 and x32 have 32 bit pointers. if (ST.isTarget64BitILP32() || !ST.is64Bit()) Ret += "-p:32:32"; - else - Ret += "-p:64:64"; // Objects on the stack ore aligned to 64 bits. // FIXME: of any size? -- 2.34.1