From 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 27 Jun 2011 18:32:37 +0000 Subject: [PATCH] Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseInfo.h | 3 +- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 4 +- lib/Target/ARM/ARMBaseRegisterInfo.h | 4 +- lib/Target/ARM/CMakeLists.txt | 3 - lib/Target/ARM/Makefile | 3 +- lib/Target/Alpha/Alpha.h | 4 +- lib/Target/Alpha/AlphaRegisterInfo.cpp | 5 +- lib/Target/Alpha/AlphaRegisterInfo.h | 4 +- lib/Target/Alpha/CMakeLists.txt | 3 - lib/Target/Alpha/Makefile | 3 +- lib/Target/Blackfin/Blackfin.h | 3 +- lib/Target/Blackfin/BlackfinRegisterInfo.cpp | 5 +- lib/Target/Blackfin/BlackfinRegisterInfo.h | 4 +- lib/Target/Blackfin/CMakeLists.txt | 3 - lib/Target/Blackfin/Makefile | 4 +- lib/Target/CellSPU/CMakeLists.txt | 3 - lib/Target/CellSPU/Makefile | 4 +- lib/Target/CellSPU/SPURegisterInfo.cpp | 4 +- lib/Target/CellSPU/SPURegisterInfo.h | 4 +- lib/Target/CellSPU/SPURegisterNames.h | 3 +- lib/Target/MBlaze/CMakeLists.txt | 3 - lib/Target/MBlaze/MBlaze.h | 3 +- lib/Target/MBlaze/MBlazeRegisterInfo.cpp | 5 +- lib/Target/MBlaze/MBlazeRegisterInfo.h | 4 +- lib/Target/MBlaze/Makefile | 4 +- lib/Target/MSP430/CMakeLists.txt | 3 - lib/Target/MSP430/MSP430.h | 3 +- lib/Target/MSP430/MSP430RegisterInfo.cpp | 4 +- lib/Target/MSP430/MSP430RegisterInfo.h | 4 +- lib/Target/MSP430/Makefile | 4 +- lib/Target/Mips/CMakeLists.txt | 3 - lib/Target/Mips/Makefile | 4 +- lib/Target/Mips/Mips.h | 3 +- lib/Target/Mips/MipsRegisterInfo.cpp | 4 +- lib/Target/Mips/MipsRegisterInfo.h | 4 +- lib/Target/PTX/CMakeLists.txt | 3 - lib/Target/PTX/Makefile | 3 - lib/Target/PTX/PTX.h | 3 +- lib/Target/PTX/PTXRegisterInfo.cpp | 6 +- lib/Target/PTX/PTXRegisterInfo.h | 3 +- lib/Target/PowerPC/CMakeLists.txt | 3 - lib/Target/PowerPC/Makefile | 4 +- lib/Target/PowerPC/PPC.h | 3 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 4 +- lib/Target/PowerPC/PPCRegisterInfo.h | 4 +- lib/Target/Sparc/CMakeLists.txt | 3 - lib/Target/Sparc/Makefile | 4 +- lib/Target/Sparc/Sparc.h | 3 +- lib/Target/Sparc/SparcRegisterInfo.cpp | 5 +- lib/Target/Sparc/SparcRegisterInfo.h | 4 +- lib/Target/SystemZ/CMakeLists.txt | 3 - lib/Target/SystemZ/Makefile | 4 +- lib/Target/SystemZ/SystemZ.h | 3 +- lib/Target/SystemZ/SystemZRegisterInfo.cpp | 5 +- lib/Target/SystemZ/SystemZRegisterInfo.h | 4 +- lib/Target/X86/CMakeLists.txt | 3 - .../X86/Disassembler/X86Disassembler.cpp | 3 +- .../X86/InstPrinter/X86ATTInstPrinter.cpp | 5 +- lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp | 4 +- lib/Target/X86/MCTargetDesc/X86TargetDesc.h | 3 +- lib/Target/X86/Makefile | 3 +- lib/Target/X86/X86RegisterInfo.cpp | 5 +- lib/Target/X86/X86RegisterInfo.h | 4 +- lib/Target/XCore/CMakeLists.txt | 3 - lib/Target/XCore/Makefile | 4 +- lib/Target/XCore/XCore.h | 3 +- lib/Target/XCore/XCoreRegisterInfo.cpp | 5 +- lib/Target/XCore/XCoreRegisterInfo.h | 4 +- utils/TableGen/RegisterInfoEmitter.cpp | 261 ++++++++++-------- utils/TableGen/RegisterInfoEmitter.h | 20 +- utils/TableGen/TableGen.cpp | 19 +- 71 files changed, 295 insertions(+), 256 deletions(-) diff --git a/lib/Target/ARM/ARMBaseInfo.h b/lib/Target/ARM/ARMBaseInfo.h index 36edbad7a60..91e9fd1f9b8 100644 --- a/lib/Target/ARM/ARMBaseInfo.h +++ b/lib/Target/ARM/ARMBaseInfo.h @@ -25,7 +25,8 @@ // Defines symbolic names for ARM registers. This defines a mapping from // register name to register number. // -#include "ARMGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "ARMGenRegisterInfo.inc" // Defines symbolic names for the ARM instructions. // diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 0e74ac0cf1c..92c98da6955 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -39,7 +39,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" -#include "ARMGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "ARMGenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index 70b6f01d6c5..b4b4059e736 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -16,7 +16,9 @@ #include "ARM.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "ARMGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "ARMGenRegisterInfo.inc" namespace llvm { class ARMSubtarget; diff --git a/lib/Target/ARM/CMakeLists.txt b/lib/Target/ARM/CMakeLists.txt index 6cb96895151..0a0ed3c741b 100644 --- a/lib/Target/ARM/CMakeLists.txt +++ b/lib/Target/ARM/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS ARM.td) -tablegen(ARMGenRegisterNames.inc -gen-register-enums) -tablegen(ARMGenRegisterDesc.inc -gen-register-desc) -tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header) tablegen(ARMGenRegisterInfo.inc -gen-register-info) tablegen(ARMGenInstrNames.inc -gen-instr-enums) tablegen(ARMGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/ARM/Makefile b/lib/Target/ARM/Makefile index 0a425143dce..9ecbd6b1b1e 100644 --- a/lib/Target/ARM/Makefile +++ b/lib/Target/ARM/Makefile @@ -12,8 +12,7 @@ LIBRARYNAME = LLVMARMCodeGen TARGET = ARM # Make sure that tblgen is run, first thing. -BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \ - ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \ +BUILT_SOURCES = ARMGenRegisterInfo.inc \ ARMGenInstrNames.inc ARMGenInstrInfo.inc \ ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \ ARMGenDAGISel.inc ARMGenSubtarget.inc \ diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h index 2c359dade29..174d2613a92 100644 --- a/lib/Target/Alpha/Alpha.h +++ b/lib/Target/Alpha/Alpha.h @@ -44,7 +44,9 @@ namespace llvm { // Defines symbolic names for Alpha registers. This defines a mapping from // register name to register number. // -#include "AlphaGenRegisterNames.inc" + +#define GET_REGINFO_ENUM +#include "AlphaGenRegisterInfo.inc" // Defines symbolic names for the Alpha instructions. // diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 5ff846eca7a..3eef05f751c 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -33,8 +33,11 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include "AlphaGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "AlphaGenRegisterInfo.inc" + using namespace llvm; AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h index ffe6cf19e21..1072bf73f19 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/lib/Target/Alpha/AlphaRegisterInfo.h @@ -15,7 +15,9 @@ #define ALPHAREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "AlphaGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "AlphaGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/Alpha/CMakeLists.txt b/lib/Target/Alpha/CMakeLists.txt index 1834b06653e..bcde4474437 100644 --- a/lib/Target/Alpha/CMakeLists.txt +++ b/lib/Target/Alpha/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Alpha.td) -tablegen(AlphaGenRegisterNames.inc -gen-register-enums) -tablegen(AlphaGenRegisterDesc.inc -gen-register-desc) -tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header) tablegen(AlphaGenRegisterInfo.inc -gen-register-info) tablegen(AlphaGenInstrNames.inc -gen-instr-enums) tablegen(AlphaGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Alpha/Makefile b/lib/Target/Alpha/Makefile index f029793d083..bd280a0e1b1 100644 --- a/lib/Target/Alpha/Makefile +++ b/lib/Target/Alpha/Makefile @@ -12,8 +12,7 @@ LIBRARYNAME = LLVMAlphaCodeGen TARGET = Alpha # Make sure that tblgen is run, first thing. -BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \ - AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \ +BUILT_SOURCES = AlphaGenRegisterInfo.inc \ AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \ AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \ AlphaGenCallingConv.inc AlphaGenSubtarget.inc diff --git a/lib/Target/Blackfin/Blackfin.h b/lib/Target/Blackfin/Blackfin.h index ec1fa8689de..3285c4f631c 100644 --- a/lib/Target/Blackfin/Blackfin.h +++ b/lib/Target/Blackfin/Blackfin.h @@ -30,7 +30,8 @@ namespace llvm { // Defines symbolic names for Blackfin registers. This defines a mapping from // register name to register number. -#include "BlackfinGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "BlackfinGenRegisterInfo.inc" // Defines symbolic names for the Blackfin instructions. #include "BlackfinGenInstrNames.inc" diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp index 6377d8e4036..aa4374488dc 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp @@ -29,8 +29,11 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "BlackfinGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "BlackfinGenRegisterInfo.inc" + using namespace llvm; BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.h b/lib/Target/Blackfin/BlackfinRegisterInfo.h index 375d277216c..86f45c17c62 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.h +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.h @@ -16,7 +16,9 @@ #define BLACKFINREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "BlackfinGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "BlackfinGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/Blackfin/CMakeLists.txt b/lib/Target/Blackfin/CMakeLists.txt index 10896c58648..c59b5a311ec 100644 --- a/lib/Target/Blackfin/CMakeLists.txt +++ b/lib/Target/Blackfin/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Blackfin.td) -tablegen(BlackfinGenRegisterNames.inc -gen-register-enums) -tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc) -tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header) tablegen(BlackfinGenRegisterInfo.inc -gen-register-info) tablegen(BlackfinGenInstrNames.inc -gen-instr-enums) tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Blackfin/Makefile b/lib/Target/Blackfin/Makefile index 8ea1dfb0676..c05d27b4cca 100644 --- a/lib/Target/Blackfin/Makefile +++ b/lib/Target/Blackfin/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMBlackfinCodeGen TARGET = Blackfin # Make sure that tblgen is run, first thing. -BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \ - BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \ - BlackfinGenInstrNames.inc \ +BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \ BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \ BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \ BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc diff --git a/lib/Target/CellSPU/CMakeLists.txt b/lib/Target/CellSPU/CMakeLists.txt index dc1f7084a58..1cce2c1a6a5 100644 --- a/lib/Target/CellSPU/CMakeLists.txt +++ b/lib/Target/CellSPU/CMakeLists.txt @@ -1,11 +1,8 @@ set(LLVM_TARGET_DEFINITIONS SPU.td) tablegen(SPUGenInstrNames.inc -gen-instr-enums) -tablegen(SPUGenRegisterNames.inc -gen-register-enums) tablegen(SPUGenAsmWriter.inc -gen-asm-writer) tablegen(SPUGenCodeEmitter.inc -gen-emitter) -tablegen(SPUGenRegisterDesc.inc -gen-register-desc) -tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SPUGenRegisterInfo.inc -gen-register-info) tablegen(SPUGenInstrInfo.inc -gen-instr-desc) tablegen(SPUGenDAGISel.inc -gen-dag-isel) diff --git a/lib/Target/CellSPU/Makefile b/lib/Target/CellSPU/Makefile index de8a9476d14..270bd6b8b38 100644 --- a/lib/Target/CellSPU/Makefile +++ b/lib/Target/CellSPU/Makefile @@ -10,10 +10,8 @@ LEVEL = ../../.. LIBRARYNAME = LLVMCellSPUCodeGen TARGET = SPU -BUILT_SOURCES = SPUGenInstrNames.inc \ +BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \ SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \ - SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \ - SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \ SPUGenInstrInfo.inc SPUGenDAGISel.inc \ SPUGenSubtarget.inc SPUGenCallingConv.inc diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 34f3f9b1ad0..a84dd5ae898 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -42,7 +42,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include "SPUGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SPUGenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index 6ecf0f28dd9..5e014f8adbf 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -16,7 +16,9 @@ #define SPU_REGISTERINFO_H #include "SPU.h" -#include "SPUGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SPUGenRegisterInfo.inc" namespace llvm { class SPUSubtarget; diff --git a/lib/Target/CellSPU/SPURegisterNames.h b/lib/Target/CellSPU/SPURegisterNames.h index 6c3afdf41fd..e557ed340a2 100644 --- a/lib/Target/CellSPU/SPURegisterNames.h +++ b/lib/Target/CellSPU/SPURegisterNames.h @@ -13,6 +13,7 @@ // Define symbolic names for Cell registers. This defines a mapping from // register name to register number. // -#include "SPUGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SPUGenRegisterInfo.inc" #endif diff --git a/lib/Target/MBlaze/CMakeLists.txt b/lib/Target/MBlaze/CMakeLists.txt index 009564e9ab0..86d030dfe8e 100644 --- a/lib/Target/MBlaze/CMakeLists.txt +++ b/lib/Target/MBlaze/CMakeLists.txt @@ -1,9 +1,6 @@ set(LLVM_TARGET_DEFINITIONS MBlaze.td) -tablegen(MBlazeGenRegisterNames.inc -gen-register-enums) -tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc) tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header) -tablegen(MBlazeGenRegisterInfo.inc -gen-register-info) tablegen(MBlazeGenInstrNames.inc -gen-instr-enums) tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc) tablegen(MBlazeGenCodeEmitter.inc -gen-emitter) diff --git a/lib/Target/MBlaze/MBlaze.h b/lib/Target/MBlaze/MBlaze.h index 00c73f06fe1..c6181f70bcf 100644 --- a/lib/Target/MBlaze/MBlaze.h +++ b/lib/Target/MBlaze/MBlaze.h @@ -39,7 +39,8 @@ namespace llvm { // Defines symbolic names for MBlaze registers. This defines a mapping from // register name to register number. -#include "MBlazeGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MBlazeGenRegisterInfo.inc" // Defines symbolic names for the MBlaze instructions. #include "MBlazeGenInstrNames.inc" diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp index f52c2e1a29a..415c83b31a4 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp @@ -36,8 +36,11 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "MBlazeGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MBlazeGenRegisterInfo.inc" + using namespace llvm; MBlazeRegisterInfo:: diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.h b/lib/Target/MBlaze/MBlazeRegisterInfo.h index 380783991ce..7ebce21d3a8 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.h +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.h @@ -17,7 +17,9 @@ #include "MBlaze.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "MBlazeGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MBlazeGenRegisterInfo.inc" namespace llvm { class MBlazeSubtarget; diff --git a/lib/Target/MBlaze/Makefile b/lib/Target/MBlaze/Makefile index 81fd5f7bba9..010885f04b9 100644 --- a/lib/Target/MBlaze/Makefile +++ b/lib/Target/MBlaze/Makefile @@ -11,9 +11,7 @@ LIBRARYNAME = LLVMMBlazeCodeGen TARGET = MBlaze # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \ - MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \ - MBlazeGenInstrNames.inc \ +BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \ MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \ MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \ MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \ diff --git a/lib/Target/MSP430/CMakeLists.txt b/lib/Target/MSP430/CMakeLists.txt index 90752fabdb6..bf58fd2e806 100644 --- a/lib/Target/MSP430/CMakeLists.txt +++ b/lib/Target/MSP430/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS MSP430.td) -tablegen(MSP430GenRegisterNames.inc -gen-register-enums) -tablegen(MSP430GenRegisterDesc.inc -gen-register-desc) -tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header) tablegen(MSP430GenRegisterInfo.inc -gen-register-info) tablegen(MSP430GenInstrNames.inc -gen-instr-enums) tablegen(MSP430GenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/MSP430/MSP430.h b/lib/Target/MSP430/MSP430.h index e74211807c0..2dabe7c0d3f 100644 --- a/lib/Target/MSP430/MSP430.h +++ b/lib/Target/MSP430/MSP430.h @@ -47,7 +47,8 @@ namespace llvm { // Defines symbolic names for MSP430 registers. // This defines a mapping from register name to register number. -#include "MSP430GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MSP430GenRegisterInfo.inc" // Defines symbolic names for the MSP430 instructions. #include "MSP430GenInstrNames.inc" diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index 397b7b403f7..0a2e93ac08b 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -25,7 +25,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" #include "llvm/Support/ErrorHandling.h" -#include "MSP430GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MSP430GenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/MSP430/MSP430RegisterInfo.h b/lib/Target/MSP430/MSP430RegisterInfo.h index e82055876f2..fb70594ab37 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.h +++ b/lib/Target/MSP430/MSP430RegisterInfo.h @@ -15,7 +15,9 @@ #define LLVM_TARGET_MSP430REGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "MSP430GenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MSP430GenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/MSP430/Makefile b/lib/Target/MSP430/Makefile index 8635646d5eb..cdbbf0ef53e 100644 --- a/lib/Target/MSP430/Makefile +++ b/lib/Target/MSP430/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMSP430CodeGen TARGET = MSP430 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \ - MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \ - MSP430GenInstrNames.inc \ +BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \ MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \ MSP430GenDAGISel.inc MSP430GenCallingConv.inc \ MSP430GenSubtarget.inc diff --git a/lib/Target/Mips/CMakeLists.txt b/lib/Target/Mips/CMakeLists.txt index f9d953639f4..aa51fbf8a57 100644 --- a/lib/Target/Mips/CMakeLists.txt +++ b/lib/Target/Mips/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Mips.td) -tablegen(MipsGenRegisterNames.inc -gen-register-enums) -tablegen(MipsGenRegisterDesc.inc -gen-register-desc) -tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header) tablegen(MipsGenRegisterInfo.inc -gen-register-info) tablegen(MipsGenInstrNames.inc -gen-instr-enums) tablegen(MipsGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Mips/Makefile b/lib/Target/Mips/Makefile index d7eab61a72e..3f5cfd7f0b6 100644 --- a/lib/Target/Mips/Makefile +++ b/lib/Target/Mips/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMipsCodeGen TARGET = Mips # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \ - MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \ - MipsGenInstrNames.inc \ +BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \ MipsGenInstrInfo.inc MipsGenAsmWriter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtarget.inc diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h index 76a26a9ba58..d296b36e658 100644 --- a/lib/Target/Mips/Mips.h +++ b/lib/Target/Mips/Mips.h @@ -35,7 +35,8 @@ namespace llvm { // Defines symbolic names for Mips registers. This defines a mapping from // register name to register number. -#include "MipsGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" // Defines symbolic names for the Mips instructions. #include "MipsGenInstrNames.inc" diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 6fdcf45e655..2b74f73fd52 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -35,7 +35,9 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "MipsGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MipsGenRegisterInfo.inc" using namespace llvm; diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 76b0035f169..646369b5966 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -16,7 +16,9 @@ #include "Mips.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "MipsGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MipsGenRegisterInfo.inc" namespace llvm { class MipsSubtarget; diff --git a/lib/Target/PTX/CMakeLists.txt b/lib/Target/PTX/CMakeLists.txt index 540af72b7cf..42b1925e9d5 100644 --- a/lib/Target/PTX/CMakeLists.txt +++ b/lib/Target/PTX/CMakeLists.txt @@ -5,10 +5,7 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv) tablegen(PTXGenDAGISel.inc -gen-dag-isel) tablegen(PTXGenInstrInfo.inc -gen-instr-desc) tablegen(PTXGenInstrNames.inc -gen-instr-enums) -tablegen(PTXGenRegisterDesc.inc -gen-register-desc) tablegen(PTXGenRegisterInfo.inc -gen-register-info) -tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header) -tablegen(PTXGenRegisterNames.inc -gen-register-enums) tablegen(PTXGenSubtarget.inc -gen-subtarget) add_llvm_target(PTXCodeGen diff --git a/lib/Target/PTX/Makefile b/lib/Target/PTX/Makefile index 1e471de3205..7c3f318aac9 100644 --- a/lib/Target/PTX/Makefile +++ b/lib/Target/PTX/Makefile @@ -17,10 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \ PTXGenDAGISel.inc \ PTXGenInstrInfo.inc \ PTXGenInstrNames.inc \ - PTXGenRegisterDesc.inc \ PTXGenRegisterInfo.inc \ - PTXGenRegisterInfo.h.inc \ - PTXGenRegisterNames.inc \ PTXGenSubtarget.inc DIRS = TargetInfo diff --git a/lib/Target/PTX/PTX.h b/lib/Target/PTX/PTX.h index ec2be9291a0..345f87a996e 100644 --- a/lib/Target/PTX/PTX.h +++ b/lib/Target/PTX/PTX.h @@ -47,7 +47,8 @@ namespace llvm { } // namespace llvm; // Defines symbolic names for PTX registers. -#include "PTXGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "PTXGenRegisterInfo.inc" // Defines symbolic names for the PTX instructions. #include "PTXGenInstrNames.inc" diff --git a/lib/Target/PTX/PTXRegisterInfo.cpp b/lib/Target/PTX/PTXRegisterInfo.cpp index 5673f963f70..06c542444f9 100644 --- a/lib/Target/PTX/PTXRegisterInfo.cpp +++ b/lib/Target/PTX/PTXRegisterInfo.cpp @@ -17,11 +17,11 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -using namespace llvm; - -#include "PTXGenRegisterDesc.inc" +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "PTXGenRegisterInfo.inc" +using namespace llvm; PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM, const TargetInstrInfo &TII) diff --git a/lib/Target/PTX/PTXRegisterInfo.h b/lib/Target/PTX/PTXRegisterInfo.h index 67e8a1b0cfb..0b63cb6d458 100644 --- a/lib/Target/PTX/PTXRegisterInfo.h +++ b/lib/Target/PTX/PTXRegisterInfo.h @@ -17,7 +17,8 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/BitVector.h" -#include "PTXGenRegisterInfo.h.inc" +#define GET_REGINFO_HEADER +#include "PTXGenRegisterInfo.inc" namespace llvm { class PTXTargetMachine; diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt index 99caa9944bd..ca5daec2102 100644 --- a/lib/Target/PowerPC/CMakeLists.txt +++ b/lib/Target/PowerPC/CMakeLists.txt @@ -1,12 +1,9 @@ set(LLVM_TARGET_DEFINITIONS PPC.td) tablegen(PPCGenInstrNames.inc -gen-instr-enums) -tablegen(PPCGenRegisterNames.inc -gen-register-enums) tablegen(PPCGenAsmWriter.inc -gen-asm-writer) tablegen(PPCGenCodeEmitter.inc -gen-emitter) tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter) -tablegen(PPCGenRegisterDesc.inc -gen-register-desc) -tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header) tablegen(PPCGenRegisterInfo.inc -gen-register-info) tablegen(PPCGenInstrInfo.inc -gen-instr-desc) tablegen(PPCGenDAGISel.inc -gen-dag-isel) diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile index 3d01792bec7..d7a57f9fa2c 100644 --- a/lib/Target/PowerPC/Makefile +++ b/lib/Target/PowerPC/Makefile @@ -12,10 +12,8 @@ LIBRARYNAME = LLVMPowerPCCodeGen TARGET = PPC # Make sure that tblgen is run, first thing. -BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \ +BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \ PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \ - PPCGenRegisterDesc.inc \ - PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \ PPCGenInstrInfo.inc PPCGenDAGISel.inc \ PPCGenSubtarget.inc PPCGenCallingConv.inc \ PPCGenMCCodeEmitter.inc diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index 92672b5b172..a8ab8f29954 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -84,7 +84,8 @@ namespace llvm { // Defines symbolic names for PowerPC registers. This defines a mapping from // register name to register number. // -#include "PPCGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "PPCGenRegisterInfo.inc" // Defines symbolic names for the PowerPC instructions. // diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 3950517ca1b..bd5c7229472 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -43,7 +43,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include "PPCGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "PPCGenRegisterInfo.inc" // FIXME (64-bit): Eventually enable by default. diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 48c25625ea9..33fe5ebcf4c 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -16,9 +16,11 @@ #define POWERPC32_REGISTERINFO_H #include "PPC.h" -#include "PPCGenRegisterInfo.h.inc" #include +#define GET_REGINFO_HEADER +#include "PPCGenRegisterInfo.inc" + namespace llvm { class PPCSubtarget; class TargetInstrInfo; diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt index 243e8897236..1a5b036c7ff 100644 --- a/lib/Target/Sparc/CMakeLists.txt +++ b/lib/Target/Sparc/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) -tablegen(SparcGenRegisterNames.inc -gen-register-enums) -tablegen(SparcGenRegisterDesc.inc -gen-register-desc) -tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SparcGenRegisterInfo.inc -gen-register-info) tablegen(SparcGenInstrNames.inc -gen-instr-enums) tablegen(SparcGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile index af7d9daa3d9..4ef15193461 100644 --- a/lib/Target/Sparc/Makefile +++ b/lib/Target/Sparc/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSparcCodeGen TARGET = Sparc # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \ - SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \ - SparcGenInstrNames.inc \ +BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \ SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index a37920d8030..0f03ca35988 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -36,7 +36,8 @@ namespace llvm { // Defines symbolic names for Sparc registers. This defines a mapping from // register name to register number. // -#include "SparcGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" // Defines symbolic names for the Sparc instructions. // diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index c63f52e9589..48ca15b590e 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -23,8 +23,11 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "SparcGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SparcGenRegisterInfo.inc" + using namespace llvm; SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 56c8068228f..ec9e63a686b 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -15,7 +15,9 @@ #define SPARCREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "SparcGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SparcGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt index 3e06109a391..5adf5e31615 100644 --- a/lib/Target/SystemZ/CMakeLists.txt +++ b/lib/Target/SystemZ/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS SystemZ.td) -tablegen(SystemZGenRegisterNames.inc -gen-register-enums) -tablegen(SystemZGenRegisterDesc.inc -gen-register-desc) -tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SystemZGenRegisterInfo.inc -gen-register-info) tablegen(SystemZGenInstrNames.inc -gen-instr-enums) tablegen(SystemZGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/SystemZ/Makefile b/lib/Target/SystemZ/Makefile index 24817152fb0..4b45615bc4f 100644 --- a/lib/Target/SystemZ/Makefile +++ b/lib/Target/SystemZ/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSystemZCodeGen TARGET = SystemZ # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \ - SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \ - SystemZGenInstrNames.inc \ +BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \ SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \ SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc diff --git a/lib/Target/SystemZ/SystemZ.h b/lib/Target/SystemZ/SystemZ.h index ea5240a10c9..8bf9fc54e80 100644 --- a/lib/Target/SystemZ/SystemZ.h +++ b/lib/Target/SystemZ/SystemZ.h @@ -53,7 +53,8 @@ namespace llvm { // Defines symbolic names for SystemZ registers. // This defines a mapping from register name to register number. -#include "SystemZGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SystemZGenRegisterInfo.inc" // Defines symbolic names for the SystemZ instructions. #include "SystemZGenInstrNames.inc" diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp index a587e1c2895..b3c76dd2350 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -25,8 +25,11 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" -#include "SystemZGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SystemZGenRegisterInfo.inc" + using namespace llvm; SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm, diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.h b/lib/Target/SystemZ/SystemZRegisterInfo.h index cd8f20fee61..2e262e1acc3 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.h +++ b/lib/Target/SystemZ/SystemZRegisterInfo.h @@ -15,7 +15,9 @@ #define SystemZREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "SystemZGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SystemZGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/X86/CMakeLists.txt b/lib/Target/X86/CMakeLists.txt index 7237ed87787..31d69af890a 100644 --- a/lib/Target/X86/CMakeLists.txt +++ b/lib/Target/X86/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS X86.td) -tablegen(X86GenRegisterNames.inc -gen-register-enums) -tablegen(X86GenRegisterDesc.inc -gen-register-desc) -tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header) tablegen(X86GenRegisterInfo.inc -gen-register-info) tablegen(X86GenDisassemblerTables.inc -gen-disassembler) tablegen(X86GenInstrNames.inc -gen-instr-enums) diff --git a/lib/Target/X86/Disassembler/X86Disassembler.cpp b/lib/Target/X86/Disassembler/X86Disassembler.cpp index d8a105e7e9d..4a0d2ec727a 100644 --- a/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -26,7 +26,8 @@ #include "llvm/Support/MemoryObject.h" #include "llvm/Support/raw_ostream.h" -#include "X86GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #include "X86GenEDInfo.inc" using namespace llvm; diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp index 68247d2f1a5..d01a6007f21 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -27,12 +27,11 @@ using namespace llvm; // Include the auto-generated portion of the assembly writer. +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR -#include "X86GenRegisterNames.inc" #include "X86GenAsmWriter.inc" -#undef PRINT_ALIAS_INSTR -#undef GET_INSTRUCTION_NAME X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) : MCInstPrinter(MAI) { diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp index 8d61745f10d..7aa77bdf6f8 100644 --- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp @@ -14,7 +14,9 @@ #include "X86TargetDesc.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" -#include "X86GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#include "X86GenRegisterInfo.inc" using namespace llvm; MCRegisterInfo *createX86MCRegisterInfo() { diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h index bcf851fb2b7..0d876dc953c 100644 --- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h +++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h @@ -23,6 +23,7 @@ extern Target TheX86_32Target, TheX86_64Target; // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // -#include "X86GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #endif diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile index 2102db7f74b..fad83438d06 100644 --- a/lib/Target/X86/Makefile +++ b/lib/Target/X86/Makefile @@ -12,8 +12,7 @@ LIBRARYNAME = LLVMX86CodeGen TARGET = X86 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \ - X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \ +BUILT_SOURCES = X86GenRegisterInfo.inc \ X86GenInstrNames.inc X86GenInstrInfo.inc \ X86GenAsmWriter.inc X86GenAsmMatcher.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index c67da211072..48f60f8934f 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -39,8 +39,11 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/CommandLine.h" -#include "X86GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "X86GenRegisterInfo.inc" + using namespace llvm; cl::opt diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 9fd6ed512a5..0c014a6b78d 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -15,7 +15,9 @@ #define X86REGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "X86GenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "X86GenRegisterInfo.inc" namespace llvm { class Type; diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt index 959e9a10913..f6e7c20c910 100644 --- a/lib/Target/XCore/CMakeLists.txt +++ b/lib/Target/XCore/CMakeLists.txt @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) -tablegen(XCoreGenRegisterNames.inc -gen-register-enums) -tablegen(XCoreGenRegisterDesc.inc -gen-register-desc) -tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header) tablegen(XCoreGenRegisterInfo.inc -gen-register-info) tablegen(XCoreGenInstrNames.inc -gen-instr-enums) tablegen(XCoreGenInstrInfo.inc -gen-instr-desc) diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile index f67ef517a17..ddc85dd09c7 100644 --- a/lib/Target/XCore/Makefile +++ b/lib/Target/XCore/Makefile @@ -12,9 +12,7 @@ LIBRARYNAME = LLVMXCoreCodeGen TARGET = XCore # Make sure that tblgen is run, first thing. -BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \ - XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \ - XCoreGenInstrNames.inc \ +BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtarget.inc diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h index 8937fbe123c..69c343dc2fb 100644 --- a/lib/Target/XCore/XCore.h +++ b/lib/Target/XCore/XCore.h @@ -32,7 +32,8 @@ namespace llvm { // Defines symbolic names for XCore registers. This defines a mapping from // register name to register number. // -#include "XCoreGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "XCoreGenRegisterInfo.inc" // Defines symbolic names for the XCore instructions. // diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 966e33b6db7..0c9473effff 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -32,8 +32,11 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "XCoreGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "XCoreGenRegisterInfo.inc" + using namespace llvm; XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h index 7a9bc9fb870..801d9eba217 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.h +++ b/lib/Target/XCore/XCoreRegisterInfo.h @@ -15,7 +15,9 @@ #define XCOREREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "XCoreGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "XCoreGenRegisterInfo.inc" namespace llvm { diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 2fcb2d49a1e..de20fb29b37 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -25,14 +25,18 @@ using namespace llvm; // runEnums - Print out enum values for all of the registers. -void RegisterInfoEmitter::runEnums(raw_ostream &OS) { - CodeGenTarget Target(Records); - CodeGenRegBank &Bank = Target.getRegBank(); +void +RegisterInfoEmitter::runEnums(raw_ostream &OS, + CodeGenTarget &Target, CodeGenRegBank &Bank) { const std::vector &Registers = Bank.getRegisters(); std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); EmitSourceFileHeader("Target Register Enum Values", OS); + + OS << "\n#ifdef GET_REGINFO_ENUM\n"; + OS << "#undef GET_REGINFO_ENUM\n"; + OS << "namespace llvm {\n\n"; if (!Namespace.empty()) @@ -63,12 +67,33 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) { if (!Namespace.empty()) OS << "}\n"; } + + const std::vector &RegisterClasses = + Target.getRegisterClasses(); + + if (!RegisterClasses.empty()) { + OS << "\n// Register classes\n"; + OS << "namespace " << RegisterClasses[0].Namespace << " {\n"; + OS << "enum {\n"; + for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { + if (i) OS << ",\n"; + OS << " " << RegisterClasses[i].getName() << "RegClassID"; + OS << " = " << i; + } + OS << "\n };\n"; + OS << "}\n"; + } + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_ENUM\n\n"; } -void RegisterInfoEmitter::runHeader(raw_ostream &OS) { +void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) { EmitSourceFileHeader("Register Information Header Fragment", OS); - CodeGenTarget Target(Records); + + OS << "\n#ifdef GET_REGINFO_HEADER\n"; + OS << "#undef GET_REGINFO_HEADER\n"; + const std::string &TargetName = Target.getName(); std::string ClassName = TargetName + "GenRegisterInfo"; @@ -100,14 +125,6 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { OS << "namespace " << RegisterClasses[0].Namespace << " { // Register classes\n"; - OS << " enum {\n"; - for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { - if (i) OS << ",\n"; - OS << " " << RegisterClasses[i].getName() << "RegClassID"; - OS << " = " << i; - } - OS << "\n };\n\n"; - for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = RegisterClasses[i]; const std::string &Name = RC.getName(); @@ -129,17 +146,125 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { OS << "} // end of namespace " << TargetName << "\n\n"; } OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_HEADER\n\n"; } // -// RegisterInfoEmitter::run - Main register file description emitter. +// runMCDesc - Print out MC register descriptions. // -void RegisterInfoEmitter::run(raw_ostream &OS) { - CodeGenTarget Target(Records); - CodeGenRegBank &RegBank = Target.getRegBank(); - RegBank.computeDerivedInfo(); +void +RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + CodeGenRegBank &RegBank) { + EmitSourceFileHeader("MC Register Information", OS); + + OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; + OS << "#undef GET_REGINFO_MC_DESC\n"; + + std::map Overlaps; + RegBank.computeOverlaps(Overlaps); + + OS << "namespace llvm {\n\n"; + + const std::string &TargetName = Target.getName(); + std::string ClassName = TargetName + "GenMCRegisterInfo"; + OS << "struct " << ClassName << " : public MCRegisterInfo {\n" + << " explicit " << ClassName << "(const MCRegisterDesc *D);\n"; + OS << "};\n"; + + OS << "\nnamespace {\n"; + + const std::vector &Regs = RegBank.getRegisters(); + + // Emit an overlap list for all registers. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister *Reg = Regs[i]; + const CodeGenRegister::Set &O = Overlaps[Reg]; + // Move Reg to the front so TRI::getAliasSet can share the list. + OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " + << getQualifiedName(Reg->TheDef) << ", "; + for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); + I != E; ++I) + if (*I != Reg) + OS << getQualifiedName((*I)->TheDef) << ", "; + OS << "0 };\n"; + } + + // Emit the empty sub-registers list + OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; + // Loop over all of the registers which have sub-registers, emitting the + // sub-registers list to memory. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Regs[i]; + if (Reg.getSubRegs().empty()) + continue; + // getSubRegs() orders by SubRegIndex. We want a topological order. + SetVector SR; + Reg.addSubRegsPreOrder(SR); + OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; + for (unsigned j = 0, je = SR.size(); j != je; ++j) + OS << getQualifiedName(SR[j]->TheDef) << ", "; + OS << "0 };\n"; + } + + // Emit the empty super-registers list + OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; + // Loop over all of the registers which have super-registers, emitting the + // super-registers list to memory. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Regs[i]; + const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); + if (SR.empty()) + continue; + OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; + for (unsigned j = 0, je = SR.size(); j != je; ++j) + OS << getQualifiedName(SR[j]->TheDef) << ", "; + OS << "0 };\n"; + } + + OS << "\n const MCRegisterDesc " << TargetName + << "RegDesc[] = { // Descriptors\n"; + OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; + + // Now that register alias and sub-registers sets have been emitted, emit the + // register descriptors now. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Regs[i]; + OS << " { \""; + OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; + if (!Reg.getSubRegs().empty()) + OS << Reg.getName() << "_SubRegsSet,\t"; + else + OS << "Empty_SubRegsSet,\t"; + if (!Reg.getSuperRegs().empty()) + OS << Reg.getName() << "_SuperRegsSet"; + else + OS << "Empty_SuperRegsSet"; + OS << " },\n"; + } + OS << " };\n"; // End of register descriptors... + + OS << "}\n\n"; // End of anonymous namespace... + + // MCRegisterInfo initialization routine. + OS << "static inline void Init" << TargetName + << "MCRegisterInfo(MCRegisterInfo *RI) {\n"; + OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " + << Regs.size()+1 << ");\n}\n\n"; + + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_MC_DESC\n\n"; +} - EmitSourceFileHeader("Register Information Source Fragment", OS); +// +// runTargetDesc - Output the target register and register file descriptions. +// +void +RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, + CodeGenRegBank &RegBank){ + EmitSourceFileHeader("Target Register and Register Classes Information", OS); + + OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; + OS << "#undef GET_REGINFO_TARGET_DESC\n"; OS << "namespace llvm {\n\n"; @@ -614,102 +739,16 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << " };\n}\n\n"; OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; } -void RegisterInfoEmitter::runDesc(raw_ostream &OS) { +void RegisterInfoEmitter::run(raw_ostream &OS) { CodeGenTarget Target(Records); CodeGenRegBank &RegBank = Target.getRegBank(); RegBank.computeDerivedInfo(); - std::map Overlaps; - RegBank.computeOverlaps(Overlaps); - - OS << "namespace llvm {\n\n"; - - const std::string &TargetName = Target.getName(); - std::string ClassName = TargetName + "GenMCRegisterInfo"; - OS << "struct " << ClassName << " : public MCRegisterInfo {\n" - << " explicit " << ClassName << "(const MCRegisterDesc *D);\n"; - OS << "};\n"; - OS << "\nnamespace {\n"; - - const std::vector &Regs = RegBank.getRegisters(); - - // Emit an overlap list for all registers. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister *Reg = Regs[i]; - const CodeGenRegister::Set &O = Overlaps[Reg]; - // Move Reg to the front so TRI::getAliasSet can share the list. - OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " - << getQualifiedName(Reg->TheDef) << ", "; - for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); - I != E; ++I) - if (*I != Reg) - OS << getQualifiedName((*I)->TheDef) << ", "; - OS << "0 };\n"; - } - - // Emit the empty sub-registers list - OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; - // Loop over all of the registers which have sub-registers, emitting the - // sub-registers list to memory. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Regs[i]; - if (Reg.getSubRegs().empty()) - continue; - // getSubRegs() orders by SubRegIndex. We want a topological order. - SetVector SR; - Reg.addSubRegsPreOrder(SR); - OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; - for (unsigned j = 0, je = SR.size(); j != je; ++j) - OS << getQualifiedName(SR[j]->TheDef) << ", "; - OS << "0 };\n"; - } - - // Emit the empty super-registers list - OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; - // Loop over all of the registers which have super-registers, emitting the - // super-registers list to memory. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Regs[i]; - const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); - if (SR.empty()) - continue; - OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; - for (unsigned j = 0, je = SR.size(); j != je; ++j) - OS << getQualifiedName(SR[j]->TheDef) << ", "; - OS << "0 };\n"; - } - - OS << "\n const MCRegisterDesc " << TargetName - << "RegDesc[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; - - // Now that register alias and sub-registers sets have been emitted, emit the - // register descriptors now. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Regs[i]; - OS << " { \""; - OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; - if (!Reg.getSubRegs().empty()) - OS << Reg.getName() << "_SubRegsSet,\t"; - else - OS << "Empty_SubRegsSet,\t"; - if (!Reg.getSuperRegs().empty()) - OS << Reg.getName() << "_SuperRegsSet"; - else - OS << "Empty_SuperRegsSet"; - OS << " },\n"; - } - OS << " };\n"; // End of register descriptors... - - OS << "}\n\n"; // End of anonymous namespace... - - // MCRegisterInfo initialization routine. - OS << "static inline void Init" << TargetName - << "MCRegisterInfo(MCRegisterInfo *RI) {\n"; - OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " - << Regs.size()+1 << ");\n}\n\n"; - - OS << "} // End llvm namespace \n"; + runEnums(OS, Target, RegBank); + runHeader(OS, Target); + runMCDesc(OS, Target, RegBank); + runTargetDesc(OS, Target, RegBank); } diff --git a/utils/TableGen/RegisterInfoEmitter.h b/utils/TableGen/RegisterInfoEmitter.h index 6bf14b259a8..d625b7d39a6 100644 --- a/utils/TableGen/RegisterInfoEmitter.h +++ b/utils/TableGen/RegisterInfoEmitter.h @@ -20,22 +20,28 @@ namespace llvm { +class CodeGenRegBank; +class CodeGenTarget; + class RegisterInfoEmitter : public TableGenBackend { RecordKeeper &Records; public: RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} - // run - Output the register file description, returning true on failure. - void run(raw_ostream &o); + // runEnums - Print out enum values for all of the registers. + void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); // runHeader - Emit a header fragment for the register info emitter. - void runHeader(raw_ostream &o); + void runHeader(raw_ostream &o, CodeGenTarget &Target); - // runEnums - Print out enum values for all of the registers. - void runEnums(raw_ostream &o); + // runMCDesc - Print out MC register descriptions. + void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); + + // runTargetDesc - Output the target register and register file descriptions. + void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); - // runDesc - Print out register descriptions. - void runDesc(raw_ostream &o); + // run - Output the register file description. + void run(raw_ostream &o); }; } // End llvm namespace diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp index b11ef6f6988..6f220c92c68 100644 --- a/utils/TableGen/TableGen.cpp +++ b/utils/TableGen/TableGen.cpp @@ -54,7 +54,7 @@ using namespace llvm; enum ActionType { PrintRecords, GenEmitter, - GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader, + GenRegisterInfo, GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher, GenARMDecoder, GenDisassembler, @@ -93,14 +93,8 @@ namespace { "Print all records to stdout (default)"), clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"), - clEnumValN(GenRegisterEnums, "gen-register-enums", - "Generate enum values for registers"), - clEnumValN(GenRegisterDesc, "gen-register-desc", - "Generate register descriptions"), clEnumValN(GenRegisterInfo, "gen-register-info", - "Generate registers & reg-classes info"), - clEnumValN(GenRegisterInfoHeader, "gen-register-info-header", - "Generate registers & reg-classes info header"), + "Generate registers and register classes info"), clEnumValN(GenInstrEnums, "gen-instr-enums", "Generate enum values for instructions"), clEnumValN(GenInstrs, "gen-instr-desc", @@ -263,18 +257,9 @@ int main(int argc, char **argv) { case GenEmitter: CodeEmitterGen(Records).run(Out.os()); break; - case GenRegisterEnums: - RegisterInfoEmitter(Records).runEnums(Out.os()); - break; - case GenRegisterDesc: - RegisterInfoEmitter(Records).runDesc(Out.os()); - break; case GenRegisterInfo: RegisterInfoEmitter(Records).run(Out.os()); break; - case GenRegisterInfoHeader: - RegisterInfoEmitter(Records).runHeader(Out.os()); - break; case GenInstrEnums: InstrEnumEmitter(Records).run(Out.os()); break; -- 2.34.1