From 73f24c9f0d9afd1fd65d544f2b7b7b7c77fc2238 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 30 Mar 2009 21:36:47 +0000 Subject: [PATCH] When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68066 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelDAGToDAG.cpp | 1 + lib/Target/X86/X86ISelLowering.cpp | 5 +++-- lib/Target/X86/X86ISelLowering.h | 5 ++++- lib/Target/X86/X86Instr64bit.td | 4 ++-- lib/Target/X86/X86InstrInfo.td | 2 ++ 5 files changed, 12 insertions(+), 5 deletions(-) diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 4afbbc67748..9caf1842eb8 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -852,6 +852,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, if (N.getResNo() != 0) break; // FALL THROUGH case ISD::MUL: + case X86ISD::MUL_IMM: // X*[3,5,9] -> X+X*[2,4,8] if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.getNode() == 0 && diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 724899b00ee..f0a9484b4b6 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -7176,6 +7176,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::UMUL: return "X86ISD::UMUL"; case X86ISD::INC: return "X86ISD::INC"; case X86ISD::DEC: return "X86ISD::DEC"; + case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; } } @@ -8458,14 +8459,14 @@ static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); else - NewMul = DAG.getNode(ISD::MUL, DL, VT, N->getOperand(0), + NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), DAG.getConstant(MulAmt1, VT)); if (isPowerOf2_64(MulAmt2)) NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); else - NewMul = DAG.getNode(ISD::MUL, DL, VT, NewMul, + NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, DAG.getConstant(MulAmt2, VT)); // Do not add new nodes to DAG combiner worklist. diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index d4bd578506c..ca4af634226 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -237,7 +237,10 @@ namespace llvm { // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. ADD, SUB, SMUL, UMUL, - INC, DEC + INC, DEC, + + // MUL_IMM - X86 specific multiply by immediate. + MUL_IMM }; } diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 73e1f9814b0..ce5a8a37032 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -36,8 +36,8 @@ def lea64_32mem : Operand { // Complex Pattern Definitions. // def lea64addr : ComplexPattern; + [add, mul, X86mul_imm, shl, or, frameindex, X86Wrapper], + []>; //===----------------------------------------------------------------------===// // Pattern fragments. diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 855d3b56112..b0f78422e7a 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -157,6 +157,8 @@ def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; +def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; + //===----------------------------------------------------------------------===// // X86 Operand Definitions. // -- 2.34.1