From 73460aea4ff6c86c4ce73ac1db125986c31e96ea Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 11 Dec 2014 23:37:34 +0000 Subject: [PATCH] R600/SI: Handle physical registers in getOpRegClass git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224079 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrInfo.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 4aa5ac889c3..9328c2c2c23 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -1242,8 +1242,13 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); const MCInstrDesc &Desc = get(MI.getOpcode()); if (MI.isVariadic() || OpNo >= Desc.getNumOperands() || - Desc.OpInfo[OpNo].RegClass == -1) - return MRI.getRegClass(MI.getOperand(OpNo).getReg()); + Desc.OpInfo[OpNo].RegClass == -1) { + unsigned Reg = MI.getOperand(OpNo).getReg(); + + if (TargetRegisterInfo::isVirtualRegister(Reg)) + return MRI.getRegClass(Reg); + return RI.getRegClass(Reg); + } unsigned RCID = Desc.OpInfo[OpNo].RegClass; return RI.getRegClass(RCID); -- 2.34.1