From 724651ab6e5efc6b4a321c6c9f58a3a716072d50 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Tue, 19 Aug 2008 01:05:33 +0000 Subject: [PATCH] Make SimpleSpiller respect subregister indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54968 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/VirtRegMap.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index c06ff71e6f4..890ecf984c6 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -241,6 +241,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; const TargetMachine &TM = MF.getTarget(); const TargetInstrInfo &TII = *TM.getInstrInfo(); + const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); // LoadedRegs - Keep track of which vregs are loaded, so that we only load @@ -261,7 +262,9 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { if (MO.isRegister() && MO.getReg()) { if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned VirtReg = MO.getReg(); + unsigned SubIdx = MO.getSubReg(); unsigned PhysReg = VRM.getPhys(VirtReg); + unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg; if (!VRM.isAssignedReg(VirtReg)) { int StackSlot = VRM.getStackSlot(VirtReg); const TargetRegisterClass* RC = @@ -286,8 +289,8 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { ++NumStores; } } - MF.getRegInfo().setPhysRegUsed(PhysReg); - MI.getOperand(i).setReg(PhysReg); + MF.getRegInfo().setPhysRegUsed(RReg); + MI.getOperand(i).setReg(RReg); } else { MF.getRegInfo().setPhysRegUsed(MO.getReg()); } -- 2.34.1