From 71a258c36bcf24be212afaca798f47346d9df77e Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Sat, 29 Aug 2009 22:19:15 +0000 Subject: [PATCH] CMOV_GR8 clobbers EFLAGS when its expansion involves an xor to set a register to 0. This fixes PR4814. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80445 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrInfo.td | 6 ++-- test/CodeGen/X86/cmov-i8-eflags.ll | 55 ++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/X86/cmov-i8-eflags.ll diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e7603103952..056335f167e 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1038,8 +1038,10 @@ let Uses = [EFLAGS] in { // X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to // emit control flow. An alternative to this is to mark i8 SELECT as Promote, // however that requires promoting the operands, and can induce additional -// i8 register pressure. -let usesCustomDAGSchedInserter = 1, isTwoAddress = 0 in +// i8 register pressure. Note that CMOV_GR8 is conservatively considered to +// clobber EFLAGS, because if one of the operands is zero, the expansion +// could involve an xor. +let usesCustomDAGSchedInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in def CMOV_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), "#CMOV_GR8 PSEUDO!", diff --git a/test/CodeGen/X86/cmov-i8-eflags.ll b/test/CodeGen/X86/cmov-i8-eflags.ll new file mode 100644 index 00000000000..e81ce581169 --- /dev/null +++ b/test/CodeGen/X86/cmov-i8-eflags.ll @@ -0,0 +1,55 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | %prcontext {setne %al} 1 | grep test | count 2 +; PR4814 + +; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional +; move without recomputing EFLAGS, because the expansion of the conditional +; move with control flow may clobber EFLAGS (e.g., with xor, to set the +; register to zero). + +; The prcontext usage above is a little awkward; the important part is that +; there's a test before the setne. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" + +@g_3 = external global i8 ; [#uses=1] +@g_96 = external global i8 ; [#uses=2] +@g_100 = external global i8 ; [#uses=2] +@_2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1] + +define i32 @main() nounwind { +entry: + %0 = load i8* @g_3, align 1 ; [#uses=2] + %1 = sext i8 %0 to i32 ; [#uses=1] + %.lobit.i = lshr i8 %0, 7 ; [#uses=1] + %tmp.i = zext i8 %.lobit.i to i32 ; [#uses=1] + %tmp.not.i = xor i32 %tmp.i, 1 ; [#uses=1] + %iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i ; [#uses=1] + %retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; [#uses=1] + %2 = icmp eq i8 %retval56.i.i, 0 ; [#uses=2] + %g_96.promoted.i = load i8* @g_96 ; [#uses=3] + %3 = icmp eq i8 %g_96.promoted.i, 0 ; [#uses=2] + br i1 %3, label %func_4.exit.i, label %bb.i.i.i + +bb.i.i.i: ; preds = %entry + %4 = volatile load i8* @g_100, align 1 ; [#uses=0] + br label %func_4.exit.i + +func_4.exit.i: ; preds = %bb.i.i.i, %entry + %.not.i = xor i1 %2, true ; [#uses=1] + %brmerge.i = or i1 %3, %.not.i ; [#uses=1] + %.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0 ; [#uses=1] + br i1 %brmerge.i, label %func_1.exit, label %bb.i.i + +bb.i.i: ; preds = %func_4.exit.i + %5 = volatile load i8* @g_100, align 1 ; [#uses=0] + br label %func_1.exit + +func_1.exit: ; preds = %bb.i.i, %func_4.exit.i + %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; [#uses=2] + store i8 %g_96.tmp.0.i, i8* @g_96 + %6 = zext i8 %g_96.tmp.0.i to i32 ; [#uses=1] + %7 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; [#uses=0] + ret i32 0 +} + +declare i32 @printf(i8* nocapture, ...) nounwind -- 2.34.1