From 6fea31e7300fe012b0b2984d6bc0338d02b054d3 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 4 Oct 2011 15:28:08 +0000 Subject: [PATCH] TableGen: Privatize CodeGenRegisterClass::TheDef and Name. When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/AsmMatcherEmitter.cpp | 6 ++++- utils/TableGen/AsmWriterEmitter.cpp | 4 ++-- utils/TableGen/CodeGenRegisters.cpp | 9 +++++--- utils/TableGen/CodeGenRegisters.h | 10 ++++++-- utils/TableGen/RegisterInfoEmitter.cpp | 32 +++++++++----------------- 5 files changed, 32 insertions(+), 29 deletions(-) diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index e43f8311a8b..8b86c23d063 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -999,6 +999,10 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { for (ArrayRef::const_iterator it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { const CodeGenRegisterClass &RC = **it; + // Def will be NULL for non-user defined register classes. + Record *Def = RC.getDef(); + if (!Def) + continue; ClassInfo *CI = RegisterSetClasses[std::set(RC.getOrder().begin(), RC.getOrder().end())]; if (CI->ValueName.empty()) { @@ -1008,7 +1012,7 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { } else CI->ValueName = CI->ValueName + "," + RC.getName(); - RegisterClassClasses.insert(std::make_pair(RC.TheDef, CI)); + RegisterClassClasses.insert(std::make_pair(Def, CI)); } // Populate the map for individual registers. diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index bb91cd0415c..3123e11f774 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -712,7 +712,7 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) { // Emit the register enum value for each RegisterClass. for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) { if (I != 0) O << ",\n"; - O << " RC_" << RegisterClasses[I]->TheDef->getName(); + O << " RC_" << RegisterClasses[I]->getName(); } O << "\n };\n"; @@ -732,7 +732,7 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) { const CodeGenRegisterClass &RC = *RegisterClasses[I]; // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); + std::string Name = RC.getName(); O << " case RC_" << Name << ":\n"; // Emit the register list now. diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 4c8d3608752..0785f70ce01 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -256,7 +256,7 @@ struct TupleExpander : SetTheory::Expander { //===----------------------------------------------------------------------===// CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) - : TheDef(R), EnumValue(-1) { + : TheDef(R), Name(R->getName()), EnumValue(-1) { // Rename anonymous register classes. if (R->getName().size() > 9 && R->getName()[9] == '.') { static unsigned AnonCounter = 0; @@ -385,8 +385,11 @@ static int TopoOrderRC(const void *PA, const void *PB) { return A->getName() < B->getName(); } -const std::string &CodeGenRegisterClass::getName() const { - return TheDef->getName(); +std::string CodeGenRegisterClass::getQualifiedName() const { + if (Namespace.empty()) + return getName(); + else + return Namespace + "::" + getName(); } // Compute sub-classes of all register classes. diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index f5759b557dc..b8d2053cf9e 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -93,8 +93,9 @@ namespace llvm { // List of super-classes, topologocally ordered to have the larger classes // first. This is the same as sorting by EnumValue. SmallVector SuperClasses; - public: Record *TheDef; + std::string Name; + public: unsigned EnumValue; std::string Namespace; std::vector VTs; @@ -106,7 +107,12 @@ namespace llvm { DenseMap SubRegClasses; std::string AltOrderSelect; - const std::string &getName() const; + // Return the Record that defined this class, or NULL if the class was + // created by TableGen. + Record *getDef() const { return TheDef; } + + const std::string &getName() const { return Name; } + std::string getQualifiedName() const; const std::vector &getValueTypes() const {return VTs;} unsigned getNumValueTypes() const { return VTs.size(); } diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 19b45f86677..f2cc36d371e 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -371,10 +371,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = *RegisterClasses[rc]; - OS << " MCRegisterClass("; - if (!RC.Namespace.empty()) - OS << RC.Namespace << "::"; - OS << RC.getName() + "RegClassID" << ", " + OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", " << '\"' << RC.getName() << "\", " << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " @@ -556,17 +553,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, SRC.at(idx-1) = i->second; // Find the register class number of i->second for SuperRegClassMap. - for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { - const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2]; - if (RC2.TheDef == i->second) { - SuperRegClassMap[rc2].insert(rc); - break; - } - } + const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second); + assert(RC2 && "Invalid register class in SubRegClasses"); + SuperRegClassMap[RC2->EnumValue].insert(rc); } // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); + std::string Name = RC.getName(); OS << " // " << Name << " Sub-register Classes...\n" @@ -589,7 +582,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, const CodeGenRegisterClass &RC = *RegisterClasses[rc]; // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); + std::string Name = RC.getName(); OS << " // " << Name << " Super-register Classes...\n" @@ -605,7 +598,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, const CodeGenRegisterClass &RC2 = *RegisterClasses[*II]; if (!Empty) OS << ", "; - OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; + OS << "&" << RC2.getQualifiedName() << "RegClass"; Empty = false; } } @@ -620,7 +613,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, const CodeGenRegisterClass &RC = *RegisterClasses[rc]; // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); + std::string Name = RC.getName(); OS << " static const unsigned " << Name << "SubclassMask[] = { "; printBitVectorAsHex(OS, RC.getSubClasses(), 32); @@ -639,7 +632,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << " static const TargetRegisterClass* const " << RC.getName() << "Superclasses[] = {\n"; for (unsigned i = 0; i != Supers.size(); ++i) - OS << " &" << getQualifiedName(Supers[i]->TheDef) << "RegClass,\n"; + OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; OS << " NULL\n };\n\n"; } @@ -675,10 +668,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << " };\n"; } OS << " const MCRegisterClass &MCR = " << Target.getName() - << "MCRegisterClasses["; - if (!RC.Namespace.empty()) - OS << RC.Namespace << "::"; - OS << RC.getName() + "RegClassID];" + << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];" << " static const ArrayRef Order[] = {\n" << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) @@ -695,7 +685,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "\nnamespace {\n"; OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) - OS << " &" << getQualifiedName(RegisterClasses[i]->TheDef) + OS << " &" << RegisterClasses[i]->getQualifiedName() << "RegClass,\n"; OS << " };\n"; OS << "}\n"; // End of anonymous namespace... -- 2.34.1