From 6d55dfaf9124c3e5e54190090478d2f6384a51d4 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Wed, 28 Aug 2013 00:34:17 +0000 Subject: [PATCH] [mips] Set isAllocatable and CoveredBySubRegs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189430 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsRegisterInfo.td | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 022a9c0c7ba..22c489090d8 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -60,6 +60,7 @@ class AFPR Enc, string n, list subregs> class AFPR64 Enc, string n, list subregs> : MipsRegWithSubRegs { let SubRegIndices = [sub_lo, sub_hi]; + let CoveredBySubRegs = 1; } // Mips 128-bit (aliased) MSA Registers @@ -294,7 +295,8 @@ def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; // * FGR32 - 32 32-bit registers (single float only mode) def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; -def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>; +def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, + Unallocatable; def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments -- 2.34.1