From 6d13144cf6086b48928af2293c4f190220a2ad3f Mon Sep 17 00:00:00 2001 From: Peizhao Ou Date: Thu, 5 Apr 2018 16:05:08 -0700 Subject: [PATCH] Reverts more unnecessary changes --- include/llvm/CodeGen/MachineBasicBlock.h | 13 ---- include/llvm/IR/BasicBlock.h | 13 ---- include/llvm/IR/Instructions.h | 10 --- lib/CodeGen/AtomicExpandPass.cpp | 81 +----------------------- lib/CodeGen/MachineBasicBlock.cpp | 2 +- lib/IR/BasicBlock.cpp | 3 +- 6 files changed, 4 insertions(+), 118 deletions(-) diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index fd786f68fb6..3d58c499823 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -124,10 +124,6 @@ private: /// is only computed once and is cached. mutable MCSymbol *CachedMCSymbol = nullptr; - // XXX-update: A flag that checks whether we can eliminate this machine basic - // block. - bool canEliminateMachineBB; - // Intrusive list support MachineBasicBlock() {} @@ -139,15 +135,6 @@ private: friend class MachineFunction; public: - // XXX-update: - void disableCanEliminateMachineBB() { - canEliminateMachineBB = false; - } - - bool getCanEliminateMachineBB() { - return canEliminateMachineBB; - } - /// Return the LLVM basic block that this instance corresponded to originally. /// Note that this may be NULL if this instance does not correspond directly /// to an LLVM basic block. diff --git a/include/llvm/IR/BasicBlock.h b/include/llvm/IR/BasicBlock.h index 94edb547f53..c6b54d308ce 100644 --- a/include/llvm/IR/BasicBlock.h +++ b/include/llvm/IR/BasicBlock.h @@ -59,9 +59,6 @@ private: InstListType InstList; Function *Parent; - // XXX-update: A flag that checks whether we can eliminate this block. - bool canEliminateBlock; - void setParent(Function *parent); friend class SymbolTableListTraits; @@ -77,16 +74,6 @@ private: Function *Parent = nullptr, BasicBlock *InsertBefore = nullptr); public: - // XXX-update: - void disableCanEliminateBlock() { - canEliminateBlock = false; - } - - bool getCanEliminateBlock() { - return canEliminateBlock; - } - - /// \brief Get the context in which this basic block lives. LLVMContext &getContext() const; diff --git a/include/llvm/IR/Instructions.h b/include/llvm/IR/Instructions.h index cc6c25974cd..28e1fd90fdf 100644 --- a/include/llvm/IR/Instructions.h +++ b/include/llvm/IR/Instructions.h @@ -228,14 +228,6 @@ public: LoadInst(Value *Ptr, const char *NameStr, bool isVolatile, BasicBlock *InsertAtEnd); - bool getHasSubsequentAcqlRMW() { - return hasSubsequentAcqlRMW_; - } - - void setHasSubsequentAcqlRMW(bool val) { - hasSubsequentAcqlRMW_ = val; - } - /// isVolatile - Return true if this is a load from a volatile memory /// location. /// @@ -314,8 +306,6 @@ private: void setInstructionSubclassData(unsigned short D) { Instruction::setInstructionSubclassData(D); } - - bool hasSubsequentAcqlRMW_; }; //===----------------------------------------------------------------------===// diff --git a/lib/CodeGen/AtomicExpandPass.cpp b/lib/CodeGen/AtomicExpandPass.cpp index 180aba78709..c3c3f6ca29d 100644 --- a/lib/CodeGen/AtomicExpandPass.cpp +++ b/lib/CodeGen/AtomicExpandPass.cpp @@ -71,33 +71,6 @@ namespace { bool isIdempotentRMW(AtomicRMWInst *AI); bool simplifyIdempotentRMW(AtomicRMWInst *AI); }; - - - // If 'LI' is a relaxed load, and it is immediately followed by a -// atomic read-modify-write that has acq_rel parameter, we don't have to do -// anything since the rmw serves as a natural barrier. -void MarkRelaxedLoadBeforeAcqrelRMW(LoadInst* LI) { - auto* BB = LI->getParent(); - auto BBI = LI->getIterator(); - for (BBI++; BBI != BB->end(); BBI++) { - Instruction* CurInst = &*BBI; - if (!CurInst) { - return; - } - if (!CurInst->isAtomic()) { - continue; - } - auto* RMW = dyn_cast(CurInst); - if (!RMW) { - return; - } - if (RMW->getOrdering() == AcquireRelease || - RMW->getOrdering() == SequentiallyConsistent) { - LI->setHasSubsequentAcqlRMW(true); - } - } -} - } char AtomicExpand::ID = 0; @@ -116,7 +89,6 @@ bool AtomicExpand::runOnFunction(Function &F) { TLI = TM->getSubtargetImpl(F)->getTargetLowering(); SmallVector AtomicInsts; - SmallVector MonotonicLoadInsts; bool MadeChange = false; // XXX-comment: Converts relaxed stores to release stores. @@ -167,56 +139,8 @@ bool AtomicExpand::runOnFunction(Function &F) { // Changing control-flow while iterating through it is a bad idea, so gather a // list of all atomic instructions before we start. for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) { - // XXX-update: For relaxed loads, change them to acquire. This includes - // relaxed loads, relaxed atomic RMW & relaxed atomic compare exchange. - if (I->isAtomic()) { - switch (I->getOpcode()) { - case Instruction::AtomicCmpXchg: { - // XXX-comment: AtomicCmpXchg in AArch64 will be translated to a - // conditional branch that contains the value of the load anyway, so - // we don't need to do anything. - /* - auto* CmpXchg = dyn_cast(&*I); - auto SuccOrdering = CmpXchg->getSuccessOrdering(); - if (SuccOrdering == Monotonic) { - CmpXchg->setSuccessOrdering(Acquire); - } else if (SuccOrdering == Release) { - CmpXchg->setSuccessOrdering(AcquireRelease); - } - */ - break; - } - case Instruction::AtomicRMW: { - // XXX-comment: Similar to AtomicCmpXchg. These instructions in - // AArch64 will be translated to a loop whose condition depends on the - // store status, which further depends on the load value. - /* - auto* RMW = dyn_cast(&*I); - if (RMW->getOrdering() == Monotonic) { - RMW->setOrdering(Acquire); - } - */ - break; - } - case Instruction::Load: { - auto* LI = dyn_cast(&*I); - if (LI->getOrdering() == Monotonic) { - /* - DEBUG(dbgs() << "Transforming relaxed loads to acquire loads: " - << *LI << '\n'); - LI->setOrdering(Acquire); - */ -// MonotonicLoadInsts.push_back(LI); - MarkRelaxedLoadBeforeAcqrelRMW(LI); - } - break; - } - default: { - break; - } - } + if (I->isAtomic()) AtomicInsts.push_back(&*I); - } } for (auto I : AtomicInsts) { @@ -232,7 +156,7 @@ bool AtomicExpand::runOnFunction(Function &F) { if (TLI->getInsertFencesForAtomic()) { if (LI && isAtLeastAcquire(LI->getOrdering())) { FenceOrdering = LI->getOrdering(); -// AddFakeConditionalBranch( + LI->setOrdering(Monotonic); IsStore = false; IsLoad = true; } else if (SI && isAtLeastRelease(SI->getOrdering())) { @@ -300,7 +224,6 @@ bool AtomicExpand::runOnFunction(Function &F) { MadeChange |= expandAtomicCmpXchg(CASI); } } - return MadeChange; } diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index 42190168742..85d544d9498 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -40,7 +40,7 @@ using namespace llvm; #define DEBUG_TYPE "codegen" MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B) - : BB(B), Number(-1), xParent(&MF), canEliminateMachineBB(true) { + : BB(B), Number(-1), xParent(&MF) { Insts.Parent = this; } diff --git a/lib/IR/BasicBlock.cpp b/lib/IR/BasicBlock.cpp index 8e3cac27f48..f61276fd436 100644 --- a/lib/IR/BasicBlock.cpp +++ b/lib/IR/BasicBlock.cpp @@ -40,8 +40,7 @@ template class llvm::SymbolTableListTraits; BasicBlock::BasicBlock(LLVMContext &C, const Twine &Name, Function *NewParent, BasicBlock *InsertBefore) - : Value(Type::getLabelTy(C), Value::BasicBlockVal), Parent(nullptr), - canEliminateBlock(true) { + : Value(Type::getLabelTy(C), Value::BasicBlockVal), Parent(nullptr) { if (NewParent) insertInto(NewParent, InsertBefore); -- 2.34.1