From 68831cbd417b7e4c47b565038a4fe9a1269d5d50 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 11 Sep 2013 10:28:16 +0000 Subject: [PATCH] [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics) The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrInfo.td | 13 ++--- lib/Target/Mips/MipsSEISelLowering.cpp | 17 +++++++ test/CodeGen/Mips/msa/3r-a.ll | 68 ++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 8 deletions(-) diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 66d7f37a71d..1294121e583 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -18,6 +18,7 @@ def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; +// Immediates def immSExt5 : ImmLeaf(Imm);}]>; def immSExt10: ImmLeaf(Imm);}]>; @@ -980,14 +981,10 @@ class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, MSA128W>, class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, MSA128D>, IsCommutable; -class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", int_mips_addv_b, MSA128B>, - IsCommutable; -class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", int_mips_addv_h, MSA128H>, - IsCommutable; -class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", int_mips_addv_w, MSA128W>, - IsCommutable; -class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", int_mips_addv_d, MSA128D>, - IsCommutable; +class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128B>, IsCommutable; +class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128H>, IsCommutable; +class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128W>, IsCommutable; +class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128D>, IsCommutable; class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", int_mips_addvi_b, MSA128B>; class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", int_mips_addvi_h, MSA128H>; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 5999e197f36..0a39dda426d 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -159,6 +159,7 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::LOAD, Ty, Legal); setOperationAction(ISD::STORE, Ty, Legal); + setOperationAction(ISD::ADD, Ty, Legal); } void MipsSETargetLowering:: @@ -799,6 +800,17 @@ static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { return DAG.getMergeValues(Vals, 2, DL); } +static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { + SDLoc DL(Op); + SDValue LHS = Op->getOperand(1); + SDValue RHS = Op->getOperand(2); + EVT ResTy = Op->getValueType(0); + + SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS); + + return Result; +} + static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { SDLoc DL(Op); SDValue Value = Op->getOperand(1); @@ -846,6 +858,11 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, return lowerDSPIntr(Op, DAG, MipsISD::MSub); case Intrinsic::mips_msubu: return lowerDSPIntr(Op, DAG, MipsISD::MSubu); + case Intrinsic::mips_addv_b: + case Intrinsic::mips_addv_h: + case Intrinsic::mips_addv_w: + case Intrinsic::mips_addv_d: + return lowerMSABinaryIntr(Op, DAG, ISD::ADD); case Intrinsic::mips_bnz_b: case Intrinsic::mips_bnz_h: case Intrinsic::mips_bnz_w: diff --git a/test/CodeGen/Mips/msa/3r-a.ll b/test/CodeGen/Mips/msa/3r-a.ll index 79b82374a9c..ed41e4759c1 100644 --- a/test/CodeGen/Mips/msa/3r-a.ll +++ b/test/CodeGen/Mips/msa/3r-a.ll @@ -443,6 +443,74 @@ declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_addv_d_test ; + +define void @addv_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2 + %2 = add <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES + ret void +} + +; CHECK: addv_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: addv.b +; CHECK: st.b +; CHECK: .size addv_b_test +; + +define void @addv_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2 + %2 = add <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES + ret void +} + +; CHECK: addv_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: addv.h +; CHECK: st.h +; CHECK: .size addv_h_test +; + +define void @addv_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2 + %2 = add <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES + ret void +} + +; CHECK: addv_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: addv.w +; CHECK: st.w +; CHECK: .size addv_w_test +; + +define void @addv_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2 + %2 = add <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES + ret void +} + +; CHECK: addv_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: addv.d +; CHECK: st.d +; CHECK: .size addv_d_test +; @llvm_mips_asub_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_asub_s_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_asub_s_b_RES = global <16 x i8> , align 16 -- 2.34.1