From 67a54d2081bb40c5e2ba14295b1c6bfd4a66e8c2 Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Mon, 24 Aug 2015 09:47:45 +0000 Subject: [PATCH] Add DAG optimisation for FP16_TO_FP The FP16_TO_FP node only uses the bottom 16 bits of its input, so the following pattern can be optimised by removing the AND: (FP16_TO_FP (AND op, 0xffff)) -> (FP16_TO_FP op) This is a common pattern for ARM targets when functions have __fp16 arguments, as they are passed as floats (so that they get passed in the correct registers), but then bitcast and truncated to ignore the top 16 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245832 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 17 ++++++++++ test/CodeGen/ARM/fp16-args.ll | 40 ++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 test/CodeGen/ARM/fp16-args.ll diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 607c3bf2336..bd02b1e156b 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -313,6 +313,7 @@ namespace { SDValue visitMGATHER(SDNode *N); SDValue visitMSCATTER(SDNode *N); SDValue visitFP_TO_FP16(SDNode *N); + SDValue visitFP16_TO_FP(SDNode *N); SDValue visitFADDForFMACombine(SDNode *N); SDValue visitFSUBForFMACombine(SDNode *N); @@ -1411,6 +1412,7 @@ SDValue DAGCombiner::visit(SDNode *N) { case ISD::MSCATTER: return visitMSCATTER(N); case ISD::MSTORE: return visitMSTORE(N); case ISD::FP_TO_FP16: return visitFP_TO_FP16(N); + case ISD::FP16_TO_FP: return visitFP16_TO_FP(N); } return SDValue(); } @@ -13122,6 +13124,21 @@ SDValue DAGCombiner::visitFP_TO_FP16(SDNode *N) { return SDValue(); } +SDValue DAGCombiner::visitFP16_TO_FP(SDNode *N) { + SDValue N0 = N->getOperand(0); + + // fold fp16_to_fp(op & 0xffff) -> fp16_to_fp(op) + if (N0->getOpcode() == ISD::AND) { + ConstantSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1)); + if (AndConst && AndConst->getAPIntValue() == 0xffff) { + return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0), + N0.getOperand(0)); + } + } + + return SDValue(); +} + /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle /// with the destination vector and a zero vector. /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> diff --git a/test/CodeGen/ARM/fp16-args.ll b/test/CodeGen/ARM/fp16-args.ll new file mode 100644 index 00000000000..31a20f85483 --- /dev/null +++ b/test/CodeGen/ARM/fp16-args.ll @@ -0,0 +1,40 @@ +; RUN: llc -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT +; RUN: llc -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv7a--none-eabi" + +define float @foo(float %a.coerce, float %b.coerce) { +entry: + %0 = bitcast float %a.coerce to i32 + %tmp.0.extract.trunc = trunc i32 %0 to i16 + %1 = bitcast i16 %tmp.0.extract.trunc to half + %2 = bitcast float %b.coerce to i32 + %tmp1.0.extract.trunc = trunc i32 %2 to i16 + %3 = bitcast i16 %tmp1.0.extract.trunc to half + %4 = fadd half %1, %3 + %5 = bitcast half %4 to i16 + %tmp5.0.insert.ext = zext i16 %5 to i32 + %6 = bitcast i32 %tmp5.0.insert.ext to float + ret float %6 +; CHECK: foo: + +; SOFT: vmov {{s[0-9]+}}, r1 +; SOFT: vmov {{s[0-9]+}}, r0 +; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vcvtb.f16.f32 {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vmov r0, {{s[0-9]+}} + +; HARD-NOT: vmov +; HARD-NOT: uxth +; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1 +; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0 +; HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; HARD: vcvtb.f16.f32 s0, {{s[0-9]+}} +; HARD-NOT: vmov +; HARD-NOT: uxth + +; CHECK: bx lr +} -- 2.34.1