From 62e87cb2415b305ca9b888a2338a6af59e74005d Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 15 Oct 2013 13:14:41 +0000 Subject: [PATCH] [mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrInfo.td | 25 ++++- lib/Target/Mips/MipsSEISelLowering.cpp | 93 +++++++++++++++++-- lib/Target/Mips/MipsSEISelLowering.h | 6 ++ .../Mips/msa/basic_operations_float.ll | 43 ++++++++- 4 files changed, 151 insertions(+), 16 deletions(-) diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index c661995bfa3..2993bf6a977 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -212,6 +212,11 @@ def vsplati32 : PatFrag<(ops node:$e0), node:$e0, node:$e0))>; def vsplati64 : PatFrag<(ops node:$e0), (v2i64 (build_vector:$v0 node:$e0, node:$e0))>; +def vsplatf32 : PatFrag<(ops node:$e0), + (v4f32 (build_vector node:$e0, node:$e0, + node:$e0, node:$e0))>; +def vsplatf64 : PatFrag<(ops node:$e0), + (v2f64 (build_vector node:$e0, node:$e0))>; class SplatPatLeaf @@ -1169,15 +1174,22 @@ class MSA_2R_DESC_BASE { dag OutOperandList = (outs ROWD:$wd); - dag InOperandList = (ins ROWS:$rs); + dag InOperandList = (ins ROS:$rs); string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); - list Pattern = [(set ROWD:$wd, (VT (OpNode ROWS:$rs)))]; + list Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; InstrItinClass Itinerary = itin; } +class MSA_2R_FILL_PSEUDO_BASE : + MipsPseudo<(outs RCWD:$wd), (ins RCWS:$fs), + [(set RCWD:$wd, (OpNode RCWS:$fs))]> { + let usesCustomInserter = 1; +} + class MSA_2RF_DESC_BASE { @@ -1828,6 +1840,11 @@ class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, MSA128WOpnd, GPR32Opnd>; +class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE; +class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE; + class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; @@ -2766,6 +2783,8 @@ def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; def FILL_B : FILL_B_ENC, FILL_B_DESC; def FILL_H : FILL_H_ENC, FILL_H_DESC; def FILL_W : FILL_W_ENC, FILL_W_DESC; +def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; +def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 955f5bd582c..c0868722f77 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -214,6 +214,7 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::BITCAST, Ty, Legal); setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); + setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); if (Ty != MVT::v8f16) { setOperationAction(ISD::FABS, Ty, Legal); @@ -835,6 +836,10 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, return emitINSERT_FW(MI, BB); case Mips::INSERT_FD_PSEUDO: return emitINSERT_FD(MI, BB); + case Mips::FILL_FW_PSEUDO: + return emitFILL_FW(MI, BB); + case Mips::FILL_FD_PSEUDO: + return emitFILL_FD(MI, BB); } } @@ -2386,8 +2391,9 @@ emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ // => // subreg_to_reg $wt:sub_lo, $fs // insve_w $wd[$n], $wd_in, $wt[0] -MachineBasicBlock * MipsSETargetLowering:: -emitINSERT_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ +MachineBasicBlock * +MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, + MachineBasicBlock *BB) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); @@ -2398,11 +2404,15 @@ emitINSERT_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0).addReg(Fs).addImm(Mips::sub_lo); + .addImm(0) + .addReg(Fs) + .addImm(Mips::sub_lo); BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) - .addReg(Wd_in).addImm(Lane).addReg(Wt); + .addReg(Wd_in) + .addImm(Lane) + .addReg(Wt); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -2412,8 +2422,9 @@ emitINSERT_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ // => // subreg_to_reg $wt:sub_64, $fs // insve_d $wd[$n], $wd_in, $wt[0] -MachineBasicBlock * MipsSETargetLowering:: -emitINSERT_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ +MachineBasicBlock * +MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, + MachineBasicBlock *BB) const { assert(Subtarget->isFP64bit()); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); @@ -2426,9 +2437,73 @@ emitINSERT_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0).addReg(Fs).addImm(Mips::sub_64); + .addImm(0) + .addReg(Fs) + .addImm(Mips::sub_64); BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) - .addReg(Wd_in).addImm(Lane).addReg(Wt); + .addReg(Wd_in) + .addImm(Lane) + .addReg(Wt); + + MI->eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +// Emit the FILL_FW pseudo instruction. +// +// fill_fw_pseudo $wd, $fs +// => +// implicit_def $wt1 +// insert_subreg $wt2:subreg_lo, $wt1, $fs +// splati.w $wd, $wt2[0] +MachineBasicBlock * +MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, + MachineBasicBlock *BB) const { + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + DebugLoc DL = MI->getDebugLoc(); + unsigned Wd = MI->getOperand(0).getReg(); + unsigned Fs = MI->getOperand(1).getReg(); + unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + + BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); + BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) + .addReg(Wt1) + .addReg(Fs) + .addImm(Mips::sub_lo); + BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); + + MI->eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +// Emit the FILL_FD pseudo instruction. +// +// fill_fd_pseudo $wd, $fs +// => +// implicit_def $wt1 +// insert_subreg $wt2:subreg_64, $wt1, $fs +// splati.d $wd, $wt2[0] +MachineBasicBlock * +MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, + MachineBasicBlock *BB) const { + assert(Subtarget->isFP64bit()); + + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + DebugLoc DL = MI->getDebugLoc(); + unsigned Wd = MI->getOperand(0).getReg(); + unsigned Fs = MI->getOperand(1).getReg(); + unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); + unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); + + BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); + BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) + .addReg(Wt1) + .addReg(Fs) + .addImm(Mips::sub_64); + BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h index 52e2053ae24..c20cbffbb21 100644 --- a/lib/Target/Mips/MipsSEISelLowering.h +++ b/lib/Target/Mips/MipsSEISelLowering.h @@ -96,6 +96,12 @@ namespace llvm { /// \brief Emit the INSERT_FD pseudo instruction MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, MachineBasicBlock *BB) const; + /// \brief Emit the FILL_FW pseudo instruction + MachineBasicBlock *emitFILL_FW(MachineInstr *MI, + MachineBasicBlock *BB) const; + /// \brief Emit the FILL_FD pseudo instruction + MachineBasicBlock *emitFILL_FD(MachineInstr *MI, + MachineBasicBlock *BB) const; }; } diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll index d045920e651..7f6db85d2ac 100644 --- a/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -2,21 +2,26 @@ @v4f32 = global <4 x float> @v2f64 = global <2 x double> +@f32 = global float 0.0 +@f64 = global double 0.0 define void @const_v4f32() nounwind { ; MIPS32: const_v4f32: store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32: lui [[R1:\$[0-9]+]], 16256 + ; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]] store volatile <4 x float> , <4 x float>*@v4f32 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32: lui [[R1:\$[0-9]+]], 18304 + ; MIPS32: ori [[R2:\$[0-9]+]], [[R1]], 128 + ; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]] store volatile <4 x float> , <4 x float>*@v4f32 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( @@ -32,7 +37,7 @@ define void @const_v2f64() nounwind { ; MIPS32: const_v2f64: store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <2 x double> , <2 x double>*@v2f64 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( @@ -56,6 +61,36 @@ define void @const_v2f64() nounwind { ; MIPS32: .size const_v2f64 } +define void @nonconst_v4f32() nounwind { + ; MIPS32: nonconst_v4f32: + + %1 = load float *@f32 + %2 = insertelement <4 x float> undef, float %1, i32 0 + %3 = insertelement <4 x float> %2, float %1, i32 1 + %4 = insertelement <4 x float> %3, float %1, i32 2 + %5 = insertelement <4 x float> %4, float %1, i32 3 + store volatile <4 x float> %5, <4 x float>*@v4f32 + ; MIPS32: lwc1 $f[[R1:[0-9]+]], 0( + ; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]] + + ret void + ; MIPS32: .size nonconst_v4f32 +} + +define void @nonconst_v2f64() nounwind { + ; MIPS32: nonconst_v2f64: + + %1 = load double *@f64 + %2 = insertelement <2 x double> undef, double %1, i32 0 + %3 = insertelement <2 x double> %2, double %1, i32 1 + store volatile <2 x double> %3, <2 x double>*@v2f64 + ; MIPS32: ldc1 $f[[R1:[0-9]+]], 0( + ; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]] + + ret void + ; MIPS32: .size nonconst_v2f64 +} + define float @extract_v4f32() nounwind { ; MIPS32: extract_v4f32: -- 2.34.1