From 627e6431eb41cb03e22b8f882bc0bc73f8308f18 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Thu, 26 Nov 2015 15:50:16 +0800 Subject: [PATCH] UPSTREAM: clk: rockchip: add mipidsi clock on rk3288 sclk_mipidsi_24m is the gating of mipi dsi phy. Change-Id: I15b3e7a17b06397eb825eb2faca37d77732c9a97 Signed-off-by: Chris Zhong Acked-by: Stephen Boyd Signed-off-by: Heiko Stuebner (cherry picked from commit a2f4c560f18edd2ffe0f15d52ce2be55cff605d2) --- drivers/clk/rockchip/clk-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 1196818a0fbd..baeb78e2cf15 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -738,7 +738,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), - GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), + GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), /* sclk_gpu gates */ GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS), -- 2.34.1