From 611c6e135910779a8d1ed6db023d87f19799f6ac Mon Sep 17 00:00:00 2001 From: Arnold Schwaighofer Date: Tue, 4 Jun 2013 22:15:46 +0000 Subject: [PATCH] ARM sched model: Add divsion, loads, branches, vfp cvt Add some generic SchedWrites and assign resources for Swift and Cortex A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrVFP.td | 6 ++- lib/Target/ARM/ARMSchedule.td | 15 +++++++ lib/Target/ARM/ARMScheduleA9.td | 7 +++ lib/Target/ARM/ARMScheduleSwift.td | 68 +++++++++++++++++++++++++++--- 4 files changed, 89 insertions(+), 7 deletions(-) diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 2380528e130..c79ffddf6b5 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -870,7 +870,8 @@ let Constraints = "$a = $dst" in { class AVConv1XInsS_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : AVConv1XI { + : AVConv1XI, + Sched<[WriteCvtFP]> { bits<5> dst; // if dp_operation then UInt(D:Vd) else UInt(Vd:D); let Inst{22} = dst{0}; @@ -881,7 +882,8 @@ class AVConv1XInsS_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, class AVConv1XInsD_Encode op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : AVConv1XI { + : AVConv1XI, + Sched<[WriteCvtFP]> { bits<5> dst; // if dp_operation then UInt(D:Vd) else UInt(Vd:D); let Inst{22} = dst{4}; diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 2d088de96e2..f25e9c2e2a3 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -69,6 +69,21 @@ def WriteCMP : SchedWrite; def WriteCMPsi : SchedWrite; def WriteCMPsr : SchedWrite; +// Division. +def WriteDiv : SchedWrite; + +// Loads. +def WriteLd : SchedWrite; +def WritePreLd : SchedWrite; + +// Branches. +def WriteBr : SchedWrite; +def WriteBrL : SchedWrite; +def WriteBrTbl : SchedWrite; + +// Fixpoint conversions. +def WriteCvtFP : SchedWrite; + // Define TII for use in SchedVariant Predicates. def : PredicateProlog<[{ const ARMBaseInstrInfo *TII = diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 9739ed20ce2..884c780399d 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -2493,4 +2493,11 @@ def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; +def : WriteRes { let Latency = 0; } + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : SchedAlias; } // SchedModel = CortexA9Model diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index 7c6df410706..c888b69a93a 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -1096,9 +1096,27 @@ let SchedModel = SwiftModel in { def SwiftUnitDiv : ProcResource<1>; // Generic resource requirements. + def SwiftWriteP0OneCycle : SchedWriteRes<[SwiftUnitP0]>; + def SwiftWriteP0TwoCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 2; } + def SwiftWriteP0FourCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 4; } + def SwiftWriteP0SixCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 6; } + def SwiftWriteP0P1FourCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> { + let Latency = 4; + } + def SwiftWriteP0P1SixCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> { + let Latency = 6; + } + def SwiftWriteP01OneCycle : SchedWriteRes<[SwiftUnitP01]>; + def SwiftWriteP1TwoCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 2; } + def SwiftWriteP1FourCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 4; } + def SwiftWriteP1SixCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 6; } + def SwiftWriteP1EightCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 8; } + def SwiftWriteP1TwelveCyc : SchedWriteRes<[SwiftUnitP1]> { let Latency = 12; } + def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>; + def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>; def SwiftWriteP01TwoCycle : SchedWriteRes<[SwiftUnitP01]> { let Latency = 2; } - def SwiftWriteP01ThreeCycleTwoUops : - SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]> { + def SwiftWriteP01ThreeCycleTwoUops : SchedWriteRes<[SwiftUnitP01, + SwiftUnitP01]> { let Latency = 3; let NumMicroOps = 2; } @@ -1107,7 +1125,23 @@ let SchedModel = SwiftModel in { let NumMicroOps = 3; let ResourceCycles = [3]; } - + // Plain load without writeback. + def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> { + let Latency = 3; + } + def SwiftWriteP2FourCycle : SchedWriteRes<[SwiftUnitP2]> { + let Latency = 4; + } + // A store does not write to a register. + def SwiftWriteP2 : SchedWriteRes<[SwiftUnitP2]> { + let Latency = 0; + } + foreach Num = 1-4 in { + def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>; + } + def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle, + SwiftWriteP01OneCycle, + SwiftWriteP2ThreeCycle]>; // 4.2.4 Arithmetic and Logical. // ALU operation register shifted by immediate variant. def SwiftWriteALUsi : SchedWriteVariant<[ @@ -1137,8 +1171,32 @@ let SchedModel = SwiftModel in { def : ReadAdvance; def : SchedAlias; + + def SwiftChooseShiftKindP01OneOrTwoCycle : SchedWriteVariant<[ + SchedVar, + SchedVar + ]>; + // 4.2.5 Integer comparison def : WriteRes; - def : WriteRes; - def : WriteRes; + def : SchedAlias; + def : SchedAlias; + // 4.2.18 Integer Divide + def : WriteRes; // Workaround. + def : InstRW < [], + (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>; + // 4.2.26 Branch + def : WriteRes { let Latency = 0; } + def : WriteRes { let Latency = 2; } + def : WriteRes { let Latency = 0; } + + // 4.2.36 Advanced SIMD and VFP, Convert + def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>; + // Fixpoint conversions. + def : WriteRes { let Latency = 4; } + // Preload. + def : WriteRes { let Latency = 0; + let ResourceCycles = [0]; + } + } -- 2.34.1