From 60d733acc5364915445239ac4f74d92c2a661135 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 9 Dec 2014 18:16:49 +0000 Subject: [PATCH] [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223800 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Hexagon/HexagonExpandPredSpillCode.cpp | 12 +-- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 10 +-- lib/Target/Hexagon/HexagonInstrInfo.cpp | 4 +- lib/Target/Hexagon/HexagonInstrInfo.td | 73 +++++++++++++++---- lib/Target/Hexagon/HexagonInstrInfoV4.td | 2 +- test/MC/Disassembler/Hexagon/xtype_pred.txt | 4 + test/MC/Hexagon/inst_cmp_eq.ll | 2 +- test/MC/Hexagon/inst_cmp_eqi.ll | 2 +- test/MC/Hexagon/inst_cmp_gt.ll | 2 +- test/MC/Hexagon/inst_cmp_gti.ll | 2 +- test/MC/Hexagon/inst_cmp_lt.ll | 2 +- test/MC/Hexagon/inst_cmp_ugt.ll | 2 +- test/MC/Hexagon/inst_cmp_ugti.ll | 2 +- test/MC/Hexagon/inst_cmp_ult.ll | 2 +- test/MC/Hexagon/inst_select.ll | 2 +- 15 files changed, 87 insertions(+), 36 deletions(-) diff --git a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp index 8ef4c3ad74e..029090d4696 100644 --- a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp +++ b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp @@ -103,7 +103,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add), HEXAGON_RESERVED_REG_1) .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr), HEXAGON_RESERVED_REG_2).addReg(SrcReg); BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw_indexed)) @@ -112,7 +112,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { } else { BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr), HEXAGON_RESERVED_REG_2).addReg(SrcReg); BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw_indexed)) @@ -121,7 +121,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { .addReg(HEXAGON_RESERVED_REG_2); } } else { - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr), HEXAGON_RESERVED_REG_2).addReg(SrcReg); BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw_indexed)). @@ -154,7 +154,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { HEXAGON_RESERVED_REG_2) .addReg(HEXAGON_RESERVED_REG_1) .addImm(0); - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp), DstReg).addReg(HEXAGON_RESERVED_REG_2); } else { BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), @@ -163,13 +163,13 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { HEXAGON_RESERVED_REG_2) .addReg(HEXAGON_RESERVED_REG_1) .addImm(0); - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp), DstReg).addReg(HEXAGON_RESERVED_REG_2); } } else { BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw), HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset); - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp), DstReg).addReg(HEXAGON_RESERVED_REG_2); } MII = MBB->erase(MI); diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index d00c1f1bdbf..d02c2f86d49 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -320,7 +320,7 @@ static unsigned doesIntrinsicContainPredicate(unsigned ID) default: return 0; case Intrinsic::hexagon_C2_tfrpr: - return Hexagon::TFR_RsPd; + return Hexagon::C2_tfrpr; case Intrinsic::hexagon_C2_and: return Hexagon::C2_and; case Intrinsic::hexagon_C2_xor: @@ -1177,7 +1177,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) { if (N->getValueType(0) == MVT::i64) { // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs). SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); - SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl, + SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl, MVT::i32, SDValue(IsIntrinsic, 0)); SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, @@ -1192,7 +1192,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) { } if (N->getValueType(0) == MVT::i32) { // Convert the zero_extend to Rs = Pd - SDNode* RsPd = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl, + SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl, MVT::i32, SDValue(IsIntrinsic, 0)); ReplaceUses(N, RsPd); @@ -1236,7 +1236,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) { Ops.push_back(SDValue(Arg, 0)); } else if (RC == &Hexagon::PredRegsRegClass) { // Do the transfer. - SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1, + SDNode *PdRs = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1, SDValue(Arg, 0)); Ops.push_back(SDValue(PdRs,0)); } else if (!RC && (dyn_cast(Arg) != nullptr)) { @@ -1293,7 +1293,7 @@ SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) { CurDAG->getTargetConstant(0, MVT::i32)); // Pd = IntReg - SDNode* Pd = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1, + SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1, SDValue(IntRegTFR, 0)); // not(Pd) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 9556fdfd83a..0c2e6dcaa2a 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -454,13 +454,13 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } if (Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::IntRegsRegClass.contains(DestReg)) { - BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg). + BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg). addReg(SrcReg, getKillRegState(KillSrc)); return; } if (Hexagon::IntRegsRegClass.contains(SrcReg) && Hexagon::PredRegsRegClass.contains(DestReg)) { - BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg). + BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg). addReg(SrcReg, getKillRegState(KillSrc)); return; } diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 8102dfff914..33539a0c012 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -893,11 +893,6 @@ def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), [(set (i1 PredRegs:$dst), (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>; -def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2), - "$dst = tstbit($src1, $src2)", - [(set (i1 PredRegs:$dst), - (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>; - //===----------------------------------------------------------------------===// // ALU32/PRED - //===----------------------------------------------------------------------===// @@ -2216,6 +2211,7 @@ def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1), //===----------------------------------------------------------------------===// // STYPE/BIT + //===----------------------------------------------------------------------===// + // clrbit. def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2), "$dst = clrbit($src1, #$src2)", @@ -2259,15 +2255,66 @@ def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2), def : Pat <(xor (i32 IntRegs:$src1), -2147483648), (TOGBIT_31 (i32 IntRegs:$src1), 31)>; +//===----------------------------------------------------------------------===// +// STYPE/BIT - +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// STYPE/PRED + +//===----------------------------------------------------------------------===// + // Predicate transfer. +let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in +def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps), + "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> { + bits<5> Rd; + bits<2> Ps; + + let IClass = 0b1000; + let Inst{27-24} = 0b1001; + let Inst{22} = 0b1; + let Inst{17-16} = Ps; + let Inst{4-0} = Rd; +} + +// Transfer general register to predicate. +let hasSideEffects = 0, isCodeGenOnly = 0 in +def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs), + "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> { + bits<2> Pd; + bits<5> Rs; + + let IClass = 0b1000; + let Inst{27-21} = 0b0101010; + let Inst{20-16} = Rs; + let Inst{1-0} = Pd; +} + let hasSideEffects = 0 in -def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1), - "$dst = $src1 /* Should almost never emit this. */", - []>; +class T_TEST_BIT_IMM MajOp> + : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5), + "$Pd = "#MnOp#"($Rs, #$u5)", + [], "", S_2op_tc_2early_SLOT23> { + bits<2> Pd; + bits<5> Rs; + bits<5> u5; + let IClass = 0b1000; + let Inst{27-24} = 0b0101; + let Inst{23-21} = MajOp; + let Inst{20-16} = Rs; + let Inst{13} = 0; + let Inst{12-8} = u5; + let Inst{1-0} = Pd; +} + +def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>; + +let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. + def: Pat<(i1 (trunc (i32 IntRegs:$Rs))), + (S2_tstbit_i IntRegs:$Rs, 0)>; +} + -def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1), - "$dst = $src1 /* Should almost never emit this. */", - [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>; //===----------------------------------------------------------------------===// // STYPE/PRED - //===----------------------------------------------------------------------===// @@ -2840,7 +2887,7 @@ def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs. def : Pat<(i1 (load ADDRriS11_2:$addr)), - (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>; + (i1 (C2_tfrrp (i32 (LDrib ADDRriS11_2:$addr))))>; // Map for truncating from 64 immediates to 32 bit immediates. def : Pat<(i32 (trunc (i64 DoubleRegs:$src))), @@ -2848,7 +2895,7 @@ def : Pat<(i32 (trunc (i64 DoubleRegs:$src))), // Map for truncating from i64 immediates to i1 bit immediates. def : Pat<(i1 (trunc (i64 DoubleRegs:$src))), - (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), + (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))))>; // Map memb(Rs) = Rdd -> memb(Rs) = Rt. diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 6b8ce21daa9..4241decc899 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -3016,7 +3016,7 @@ def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))), // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd let AddedComplexity = 100 in def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))), - (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>; + (i1 (C2_tfrrp (i32 (LDb_GP_V4 tglobaladdr:$global))))>; // When the Interprocedural Global Variable optimizer realizes that a certain // global variable takes only two constant values, it shrinks the global to diff --git a/test/MC/Disassembler/Hexagon/xtype_pred.txt b/test/MC/Disassembler/Hexagon/xtype_pred.txt index 0ef3081f87b..1052d60ea49 100644 --- a/test/MC/Disassembler/Hexagon/xtype_pred.txt +++ b/test/MC/Disassembler/Hexagon/xtype_pred.txt @@ -8,5 +8,9 @@ # CHECK: p3 = cmp.gtu(r21:20, r31:30) 0x10 0xc3 0x00 0x86 # CHECK: r17:16 = mask(p3) +0x03 0xc0 0x45 0x85 +# CHECK: p3 = r5 +0x05 0xc0 0x43 0x89 +# CHECK: r5 = p3 0x11 0xc2 0x03 0x89 # CHECK: r17 = vitpack(p3, p2) \ No newline at end of file diff --git a/test/MC/Hexagon/inst_cmp_eq.ll b/test/MC/Hexagon/inst_cmp_eq.ll index 1904cf33616..113db631fa9 100644 --- a/test/MC/Hexagon/inst_cmp_eq.ll +++ b/test/MC/Hexagon/inst_cmp_eq.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: 0000 004100f2 00400000 00c09f52 +; CHECK: 0000 004100f2 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_cmp_eqi.ll b/test/MC/Hexagon/inst_cmp_eqi.ll index 78c92902350..70c4c308e1f 100644 --- a/test/MC/Hexagon/inst_cmp_eqi.ll +++ b/test/MC/Hexagon/inst_cmp_eqi.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a) ret i1 %1 } -; CHECK: 0000 40450075 00400000 00c09f52 +; CHECK: 0000 40450075 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_cmp_gt.ll b/test/MC/Hexagon/inst_cmp_gt.ll index 055129b4cb7..85fedbfb503 100644 --- a/test/MC/Hexagon/inst_cmp_gt.ll +++ b/test/MC/Hexagon/inst_cmp_gt.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: 0000 004140f2 00400000 00c09f52 +; CHECK: 0000 004140f2 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_cmp_gti.ll b/test/MC/Hexagon/inst_cmp_gti.ll index 36828cc4209..18ba3e463ef 100644 --- a/test/MC/Hexagon/inst_cmp_gti.ll +++ b/test/MC/Hexagon/inst_cmp_gti.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a) ret i1 %1 } -; CHECK: 0000 40454075 00400000 00c09f52 +; CHECK: 0000 40454075 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_cmp_lt.ll b/test/MC/Hexagon/inst_cmp_lt.ll index 32411baf2a8..3a7618421e3 100644 --- a/test/MC/Hexagon/inst_cmp_lt.ll +++ b/test/MC/Hexagon/inst_cmp_lt.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: 0000 004041f2 00400000 00c09f52 +; CHECK: 0000 004041f2 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_cmp_ugt.ll b/test/MC/Hexagon/inst_cmp_ugt.ll index c887bbff951..096536f54a7 100644 --- a/test/MC/Hexagon/inst_cmp_ugt.ll +++ b/test/MC/Hexagon/inst_cmp_ugt.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: 0000 004160f2 00400000 00c09f52 +; CHECK: 0000 004160f2 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_cmp_ugti.ll b/test/MC/Hexagon/inst_cmp_ugti.ll index 459b5bf77d3..a83583457d1 100644 --- a/test/MC/Hexagon/inst_cmp_ugti.ll +++ b/test/MC/Hexagon/inst_cmp_ugti.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a) ret i1 %1 } -; CHECK: 0000 40458075 00400000 00c09f52 +; CHECK: 0000 40458075 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_cmp_ult.ll b/test/MC/Hexagon/inst_cmp_ult.ll index 8811767aff0..4323fa0834d 100644 --- a/test/MC/Hexagon/inst_cmp_ult.ll +++ b/test/MC/Hexagon/inst_cmp_ult.ll @@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: 0000 004061f2 00400000 00c09f52 +; CHECK: 0000 004061f2 00404089 00c09f52 diff --git a/test/MC/Hexagon/inst_select.ll b/test/MC/Hexagon/inst_select.ll index c3a11082f5f..7e88c65a818 100644 --- a/test/MC/Hexagon/inst_select.ll +++ b/test/MC/Hexagon/inst_select.ll @@ -7,4 +7,4 @@ define i32 @foo (i1 %a, i32 %b, i32 %c) ret i32 %1 } -; CHECK: 0000 00400000 004201f4 00c09f52 +; CHECK: 0000 00400085 004201f4 00c09f52 -- 2.34.1