From 5a3b0cd52ee38b67fc01b1c8dd843cfcbe03a5e9 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Thu, 7 Jan 2016 20:17:36 +0800 Subject: [PATCH] UPSTREAM: clk: rockchip: rk3036: rename emac ext source clock There is only support rmii in the RK3036, so we should use the correct ext clock name as described in the TRM. Change-Id: Idf1ba727690f364f7705f15a8dac1b570c773044 Signed-off-by: Xing Zheng [update dt-binding document as well] Signed-off-by: Heiko Stuebner Signed-off-by: Caesar Wang (cherry picked from git.kernel.org next/linux-next.git master commit 01b4557d30e95c64cfdc96025e75207647524ec2) --- .../bindings/clock/rockchip,rk3036-cru.txt | 56 +++++++++++++++++++ drivers/clk/rockchip/clk-rk3036.c | 2 +- 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file mode 100644 index 000000000000..20df350b9ef3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt @@ -0,0 +1,56 @@ +* Rockchip RK3036 Clock and Reset Unit + +The RK3036 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3036-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "rmii_clkin" - external EMAC clock - optional + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@20060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + }; diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 72126b74c16a..0cefb0007033 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -136,7 +136,7 @@ PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" }; PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; -PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" }; +PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" }; PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" }; static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = { -- 2.34.1