From 596cfabbc47ba32497d2674767f9c7d71ca9f067 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Mon, 19 Jan 2015 18:33:58 +0000 Subject: [PATCH] [Hexagon] Converting remaining ALU32/ALU intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226480 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.td | 2 + lib/Target/Hexagon/HexagonIntrinsics.td | 59 +++++++++++----------- lib/Target/Hexagon/HexagonOperands.td | 6 +++ test/CodeGen/Hexagon/intrinsics-alu32-2.ll | 22 ++++++++ 4 files changed, 60 insertions(+), 29 deletions(-) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 69a3a34a7ca..128cb0d751d 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -29,6 +29,8 @@ def F64 : PatLeaf<(f64 DoubleRegs:$R)>; // 64-bit value. def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>; +def HiReg: OutPatFrag<(ops node:$Rs), + (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>; // SDNode for converting immediate C to C-1. def DEC_CONST_SIGNED : SDNodeXForm + : Pat <(IntID imm:$Is), + (MI imm:$Is)>; + +class T_R_pat + : Pat <(IntID I32:$Rs), + (MI I32:$Rs)>; + class T_RI_pat > : Pat<(IntID I32:$Rs, ImmPred:$It), (MI I32:$Rs, ImmPred:$It)>; @@ -237,6 +245,28 @@ def : T_RI_pat; def : T_RR_pat; def : T_RR_pat; +// Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32) +def : Pat <(int_hexagon_A2_not (I32:$Rs)), + (SUB_ri -1, IntRegs:$Rs)>; + +// Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32) +def : Pat <(int_hexagon_A2_neg IntRegs:$Rs), + (SUB_ri 0, IntRegs:$Rs)>; + +// Transfer immediate +def : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is), + (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>; +def : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is), + (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>; + +// Transfer Register/immediate. +def : T_R_pat ; +def : T_I_pat ; + +// Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32) +def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src), + (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>; + // // ALU 32 types. // @@ -2078,29 +2108,6 @@ class di_LDInstPI_diu4 [], "$src1 = $dst">; -/******************************************************************** -* ALU32/ALU * -*********************************************************************/ - - -// ALU32 / ALU / Negate. -def HEXAGON_A2_neg: - si_ALU32_si <"neg", int_hexagon_A2_neg>; - -// ALU32 / ALU / Transfer Immediate. -def HEXAGON_A2_tfril: - si_lo_ALU32_siu16 <"", int_hexagon_A2_tfril>; -def HEXAGON_A2_tfrih: - si_hi_ALU32_siu16 <"", int_hexagon_A2_tfrih>; -def HEXAGON_A2_tfrsi: - si_ALU32_s16 <"", int_hexagon_A2_tfrsi>; -def HEXAGON_A2_tfrpi: - di_ALU32_s8 <"", int_hexagon_A2_tfrpi>; - -// ALU32 / ALU / Transfer Register. -def HEXAGON_A2_tfr: - si_ALU32_si_tfr <"", int_hexagon_A2_tfr>; - /******************************************************************** * ALU32/PERM * *********************************************************************/ @@ -2841,12 +2848,6 @@ def HEXAGON_A2_absp: def HEXAGON_A2_abssat: si_SInst_si_sat <"abs", int_hexagon_A2_abssat>; -// STYPE / ALU / Negate. -def HEXAGON_A2_negp: - di_SInst_di <"neg", int_hexagon_A2_negp>; -def HEXAGON_A2_negsat: - si_SInst_si_sat <"neg", int_hexagon_A2_negsat>; - // STYPE / ALU / Logical Not. def HEXAGON_A2_notp: di_SInst_di <"not", int_hexagon_A2_notp>; diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td index 5a6de0ae274..51e61461423 100644 --- a/lib/Target/Hexagon/HexagonOperands.td +++ b/lib/Target/Hexagon/HexagonOperands.td @@ -259,6 +259,12 @@ def u16_s8ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<16,8>(v); }]>; +def u16_0ImmPred : PatLeaf<(i32 imm), [{ + // True if the immediate fits in a 16-bit unsigned field. + int64_t v = (int64_t)N->getSExtValue(); + return isUInt<16>(v); +}]>; + def u11_3ImmPred : PatLeaf<(i32 imm), [{ // True if the immediate fits in a 14-bit unsigned field, and the lowest // three bits are 0. diff --git a/test/CodeGen/Hexagon/intrinsics-alu32-2.ll b/test/CodeGen/Hexagon/intrinsics-alu32-2.ll index 6fd32e832b0..8da27eef58b 100644 --- a/test/CodeGen/Hexagon/intrinsics-alu32-2.ll +++ b/test/CodeGen/Hexagon/intrinsics-alu32-2.ll @@ -107,6 +107,26 @@ entry: ret void } +; CHECK: r{{[0-9]+}}.l{{ *}}={{ *}}#48242 + +define void @test11() #0 { +entry: + %0 = load i32* @d, align 4 + %1 = tail call i32 @llvm.hexagon.A2.tfril(i32 %0, i32 48242) + store i32 %1, i32* @d, align 4 + ret void +} + +; CHECK: r{{[0-9]+}}.h{{ *}}={{ *}}#50826 + +define void @test12() #0 { +entry: + %0 = load i32* @d, align 4 + %1 = tail call i32 @llvm.hexagon.A2.tfrih(i32 %0, i32 50826) + store i32 %1, i32* @d, align 4 + ret void +} + declare i32 @llvm.hexagon.A2.add(i32, i32) #1 declare i32 @llvm.hexagon.A2.sub(i32, i32) #1 declare i32 @llvm.hexagon.A2.and(i32, i32) #1 @@ -117,3 +137,5 @@ declare i32 @llvm.hexagon.A2.addi(i32, i32) #1 declare i32 @llvm.hexagon.A2.andir(i32, i32) #1 declare i32 @llvm.hexagon.A2.orir(i32, i32) #1 declare i32 @llvm.hexagon.A2.subri(i32, i32) +declare i32 @llvm.hexagon.A2.tfril(i32, i32) #1 +declare i32 @llvm.hexagon.A2.tfrih(i32, i32) #1 -- 2.34.1