From 57e80129b9d58e29dde5bdeca2a2a9501597cdd5 Mon Sep 17 00:00:00 2001 From: Kai Nacke Date: Tue, 20 Jan 2015 16:10:51 +0000 Subject: [PATCH] [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226573 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 70 ++++++++++++++++++++++++++++ lib/Target/Mips/MipsInstrFormats.td | 13 ++++++ test/CodeGen/Mips/octeon.ll | 72 +++++++++++++++++++++++++++++ test/MC/Mips/octeon-instructions.s | 9 ++++ 4 files changed, 164 insertions(+) diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index bfe2ba01195..d32ac1b11b8 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -16,6 +16,10 @@ //===----------------------------------------------------------------------===// // Unsigned Operand +def uimm5_64 : Operand { + let PrintMethod = "printUnsignedImm"; +} + def uimm16_64 : Operand { let PrintMethod = "printUnsignedImm"; } @@ -41,6 +45,38 @@ def immSExt10_64 : PatLeaf<(i64 imm), def immZExt16_64 : PatLeaf<(i64 imm), [{ return isInt<16>(N->getZExtValue()); }]>; +def immZExt5_64 : ImmLeaf; + +// Transformation function: get log2 of low 32 bits of immediate +def Log2LO : SDNodeXFormgetZExtValue())); +}]>; + +// Transformation function: get log2 of high 32 bits of immediate +def Log2HI : SDNodeXFormgetZExtValue() >> 32))); +}]>; + +// Predicate: True if immediate is a power of 2 and fits 32 bits +def PowerOf2LO : PatLeaf<(imm), [{ + if (N->getValueType(0) == MVT::i64) { + uint64_t Imm = N->getZExtValue(); + return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; + } + else + return false; +}]>; + +// Predicate: True if immediate is a power of 2 and exceeds 32 bits +def PowerOf2HI : PatLeaf<(imm), [{ + if (N->getValueType(0) == MVT::i64) { + uint64_t Imm = N->getZExtValue(); + return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; + } + else + return false; +}]>; + //===----------------------------------------------------------------------===// // Instructions specific format //===----------------------------------------------------------------------===// @@ -305,12 +341,34 @@ class SetCC64_I: let TwoOperandAliasConstraint = "$rt = $rs"; } +class CBranchBitNum shift = 1> : + InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset), + !strconcat(opstr, "\t$rs, $p, $offset"), + [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), + bb:$offset)], IIBranch, FrmI, opstr> { + let isBranch = 1; + let isTerminator = 1; + let hasDelaySlot = 1; + let Defs = [AT]; +} + // Unsigned Byte Add let Pattern = [(set GPR64Opnd:$rd, (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, ADD_FM<0x1c, 0x28>; +// Branch on Bit Clear /+32 +def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>; +def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, 0x100000000>, + BBIT_FM<0x36>; + +// Branch on Bit Set /+32 +def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd>, BBIT_FM<0x3a>; +def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, 0x100000000>, + BBIT_FM<0x3e>; + // Multiply Doubleword to GPR let Defs = [HI0, LO0, P0, P1, P2] in def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, @@ -440,6 +498,18 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), // bswap MipsPattern def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; +// Octeon bbit0/bbit1 MipsPattern +let Predicates = [HasMips64, HasCnMips] in { +def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), + (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; +def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), + (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; +def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), + (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; +def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), + (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; +} + //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index d8dae25aca9..8cc16037351 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -297,6 +297,19 @@ class BGEZ_FM op, bits<5> funct> : StdArch { let Inst{15-0} = offset; } +class BBIT_FM op> : StdArch { + bits<5> rs; + bits<5> p; + bits<16> offset; + + bits<32> Inst; + + let Inst{31-26} = op; + let Inst{25-21} = rs; + let Inst{20-16} = p; + let Inst{15-0} = offset; +} + class SLTI_FM op> : StdArch { bits<5> rt; bits<5> rs; diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll index 9d82b74f5b7..f7fbfb1f6e6 100644 --- a/test/CodeGen/Mips/octeon.ll +++ b/test/CodeGen/Mips/octeon.ll @@ -93,3 +93,75 @@ entry: %res2 = zext i1 %res to i64 ret i64 %res2 } + +define i64 @bbit0(i64 %a) nounwind { +entry: +; OCTEON-LABEL: bbit0: +; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]] +; MIPS64-LABEL: bbit0: +; MIPS64: andi $[[T0:[0-9]+]], $4, 8 +; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]] + %bit = and i64 %a, 8 + %res = icmp eq i64 %bit, 0 + br i1 %res, label %endif, label %if +if: + ret i64 48 + +endif: + ret i64 12 +} + +define i64 @bbit032(i64 %a) nounwind { +entry: +; OCTEON-LABEL: bbit032: +; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]] +; MIPS64-LABEL: bbit032: +; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 +; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 +; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] +; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]] + %bit = and i64 %a, 34359738368 + %res = icmp eq i64 %bit, 0 + br i1 %res, label %endif, label %if +if: + ret i64 48 + +endif: + ret i64 12 +} + +define i64 @bbit1(i64 %a) nounwind { +entry: +; OCTEON-LABEL: bbit1: +; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]] +; MIPS64-LABEL: bbit1: +; MIPS64: andi $[[T0:[0-9]+]], $4, 8 +; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]] + %bit = and i64 %a, 8 + %res = icmp ne i64 %bit, 0 + br i1 %res, label %endif, label %if +if: + ret i64 48 + +endif: + ret i64 12 +} + +define i64 @bbit132(i64 %a) nounwind { +entry: +; OCTEON-LABEL: bbit132: +; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]] +; MIPS64-LABEL: bbit132: +; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 +; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 +; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] +; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]] + %bit = and i64 %a, 34359738368 + %res = icmp ne i64 %bit, 0 + br i1 %res, label %endif, label %if +if: + ret i64 48 + +endif: + ret i64 12 +} diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s index 2922744c907..e98bbe40f68 100644 --- a/test/MC/Mips/octeon-instructions.s +++ b/test/MC/Mips/octeon-instructions.s @@ -3,6 +3,10 @@ # CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28] # CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28] # CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28] +# CHECK: bbit0 $19, 22, foo # encoding: [0xca,0x76,A,A] +# CHECK: bbit032 $fp, 11, foo # encoding: [0xdb,0xcb,A,A] +# CHECK: bbit1 $3, 31, foo # encoding: [0xe8,0x7f,A,A] +# CHECK: bbit132 $24, 10, foo # encoding: [0xfb,0x0a,A,A] # CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2] # CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72] # CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3] @@ -46,9 +50,14 @@ # CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f] # CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f] +foo: baddu $9, $6, $7 baddu $17, $18, $19 baddu $2, $3 + bbit0 $19, 22, foo + bbit032 $30, 11, foo + bbit1 $3, 31, foo + bbit132 $24, 10, foo cins $25, $10, 22, 2 cins $9, 17, 29 cins32 $15, $2, 18, 8 -- 2.34.1