From 5679ec3b528fb897739251b1f66037767ce2f208 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 23 Oct 2011 22:18:24 +0000 Subject: [PATCH] Add X86 SARX, SHRX, and SHLX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrShiftRotate.td | 50 +++++++++++++++-------- test/MC/Disassembler/X86/simple-tests.txt | 36 ++++++++++++++++ test/MC/Disassembler/X86/x86-32.txt | 18 ++++++++ test/MC/X86/x86_64-bmi-encoding.s | 49 ++++++++++++++++++++++ 4 files changed, 135 insertions(+), 18 deletions(-) diff --git a/lib/Target/X86/X86InstrShiftRotate.td b/lib/Target/X86/X86InstrShiftRotate.td index a32f0665d30..58cf6e39c42 100644 --- a/lib/Target/X86/X86InstrShiftRotate.td +++ b/lib/Target/X86/X86InstrShiftRotate.td @@ -744,24 +744,38 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem, } // Defs = [EFLAGS] -let Predicates = [HasBMI2], neverHasSideEffects = 1 in { - def RORX32ri : Ii8<0xF0, MRMSrcReg, (outs GR32:$dst), - (ins GR32:$src1, i8imm:$src2), - "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX; +multiclass bmi_rotate { +let neverHasSideEffects = 1 in { + def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX; let mayLoad = 1 in - def RORX32mi : Ii8<0xF0, MRMSrcMem, (outs GR32:$dst), - (ins i32mem:$src1, i8imm:$src2), - "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX; - - def RORX64ri : Ii8<0xF0, MRMSrcReg, (outs GR64:$dst), - (ins GR64:$src1, i8imm:$src2), - "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX, VEX_W; + def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), + (ins x86memop:$src1, i8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX; +} +} + +multiclass bmi_shift { +let neverHasSideEffects = 1 in { + def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX_4VOp3; let mayLoad = 1 in - def RORX64mi : Ii8<0xF0, MRMSrcMem, (outs GR64:$dst), - (ins i64mem:$src1, i8imm:$src2), - "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, - TAXD, VEX, VEX_W; + def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX_4VOp3; +} +} + +let Predicates = [HasBMI2] in { + defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; + defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; + defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; + defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; + defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; + defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; + defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize; + defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W; } diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 229c10dc1d7..05a57d7d272 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -611,3 +611,39 @@ # CHECK: rorxq $63, (%rax), %r10 0xc4 0x63 0xfb 0xf0 0x10 0x3f + +# CHECK: shlxl %r12d, (%rax), %r10d +0xc4 0x62 0x19 0xf7 0x10 + +# CHECK: shlxl %r12d, %r11d, %r10d +0xc4 0x42 0x19 0xf7 0xd3 + +# CHECK: shlxq %r12, (%rax), %r10 +0xc4 0x62 0x99 0xf7 0x10 + +# CHECK: shlxq %r12, %r11, %r10 +0xc4 0x42 0x99 0xf7 0xd3 + +# CHECK: sarxl %r12d, (%rax), %r10d +0xc4 0x62 0x1a 0xf7 0x10 + +# CHECK: sarxl %r12d, %r11d, %r10d +0xc4 0x42 0x1a 0xf7 0xd3 + +# CHECK: sarxq %r12, (%rax), %r10 +0xc4 0x62 0x9a 0xf7 0x10 + +# CHECK: sarxq %r12, %r11, %r10 +0xc4 0x42 0x9a 0xf7 0xd3 + +# CHECK: shrxl %r12d, (%rax), %r10d +0xc4 0x62 0x1b 0xf7 0x10 + +# CHECK: shrxl %r12d, %r11d, %r10d +0xc4 0x42 0x1b 0xf7 0xd3 + +# CHECK: shrxq %r12, (%rax), %r10 +0xc4 0x62 0x9b 0xf7 0x10 + +# CHECK: shrxq %r12, %r11, %r10 +0xc4 0x42 0x9b 0xf7 0xd3 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 10d3c1fea6c..5d5ee5dc058 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -549,3 +549,21 @@ # CHECK: rorxl $31, (%eax), %edx 0xc4 0xe3 0x7b 0xf0 0x10 0x1f + +# CHECK: shlxl %esi, (%eax), %edx +0xc4 0xe2 0x09 0xf7 0x10 + +# CHECK: shlxl %esi, %ebx, %edx +0xc4 0xe2 0x09 0xf7 0xd3 + +# CHECK: sarxl %esi, (%eax), %edx +0xc4 0xe2 0x0a 0xf7 0x10 + +# CHECK: sarxl %esi, %ebx, %edx +0xc4 0xe2 0x0a 0xf7 0xd3 + +# CHECK: shrxl %esi, (%eax), %edx +0xc4 0xe2 0x0b 0xf7 0x10 + +# CHECK: shrxl %esi, %ebx, %edx +0xc4 0xe2 0x0b 0xf7 0xd3 diff --git a/test/MC/X86/x86_64-bmi-encoding.s b/test/MC/X86/x86_64-bmi-encoding.s index aa5aa9aa202..3e69d4af0b7 100644 --- a/test/MC/X86/x86_64-bmi-encoding.s +++ b/test/MC/X86/x86_64-bmi-encoding.s @@ -151,3 +151,52 @@ // CHECK: rorxq $63, (%rax), %r10 // CHECK: encoding: [0xc4,0x63,0xfb,0xf0,0x10,0x3f] rorxq $63, (%rax), %r10 + +// CHECK: shlxl %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x19,0xf7,0x10] + shlxl %r12d, (%rax), %r10d + +// CHECK: shlxl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x19,0xf7,0xd3] + shlxl %r12d, %r11d, %r10d + +// CHECK: shlxq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x99,0xf7,0x10] + shlxq %r12, (%rax), %r10 + +// CHECK: shlxq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x99,0xf7,0xd3] + shlxq %r12, %r11, %r10 + +// CHECK: sarxl %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x1a,0xf7,0x10] + sarxl %r12d, (%rax), %r10d + +// CHECK: sarxl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x1a,0xf7,0xd3] + sarxl %r12d, %r11d, %r10d + +// CHECK: sarxq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x9a,0xf7,0x10] + sarxq %r12, (%rax), %r10 + +// CHECK: sarxq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x9a,0xf7,0xd3] + sarxq %r12, %r11, %r10 + +// CHECK: shrxl %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x1b,0xf7,0x10] + shrxl %r12d, (%rax), %r10d + +// CHECK: shrxl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x1b,0xf7,0xd3] + shrxl %r12d, %r11d, %r10d + +// CHECK: shrxq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x9b,0xf7,0x10] + shrxq %r12, (%rax), %r10 + +// CHECK: shrxq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x9b,0xf7,0xd3] + shrxq %r12, %r11, %r10 + -- 2.34.1