From 54c47c1ce94b9e549ef768e80fd004788d13ce85 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sat, 18 Jun 2011 03:08:20 +0000 Subject: [PATCH] Remove MethodProtos/MethodBodies and allocation_order_begin/end. Targets that need to change the default allocation order should use the AltOrders mechanism instead. See the X86 and ARM targets for examples. The allocation_order_begin() and allocation_order_end() methods have been replaced with getRawAllocationOrder(), and there is further support functions in RegisterClassInfo. It is no longer possible to insert arbitrary code into generated register classes. This is a feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/Target.td | 6 ------ include/llvm/Target/TargetRegisterInfo.h | 27 +----------------------- utils/TableGen/CodeGenRegisters.cpp | 2 -- utils/TableGen/CodeGenRegisters.h | 2 +- utils/TableGen/RegisterInfoEmitter.cpp | 3 +-- 5 files changed, 3 insertions(+), 37 deletions(-) diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 915879202ca..a0331705eb4 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -133,12 +133,6 @@ class RegisterClass regTypes, int alignment, // model instruction operand constraints, and should have isAllocatable = 0. bit isAllocatable = 1; - // MethodProtos/MethodBodies - These members can be used to insert arbitrary - // code into a generated register class. The normal usage of this is to - // overload virtual methods. - code MethodProtos = [{}]; - code MethodBodies = [{}]; - // AltOrders - List of alternative allocation orders. The default order is // MemberList itself, and that is good enough for most targets since the // register allocators automatically remove reserved registers and move diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index feb09292feb..840b0487047 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -237,29 +237,6 @@ public: return SuperClasses[0] != 0; } - /// allocation_order_begin/end - These methods define a range of registers - /// which specify the registers in this class that are valid to register - /// allocate, and the preferred order to allocate them in. For example, - /// callee saved registers should be at the end of the list, because it is - /// cheaper to allocate caller saved registers. - /// - /// These methods take a MachineFunction argument, which can be used to tune - /// the allocatable registers based on the characteristics of the function, - /// subtarget, or other criteria. - /// - /// Register allocators should account for the fact that an allocation - /// order iterator may return a reserved register and always check - /// if the register is allocatable (getAllocatableSet()) before using it. - /// - /// By default, these methods return all registers in the class. - /// - virtual iterator allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - virtual iterator allocation_order_end(const MachineFunction &MF) const { - return end(); - } - /// getRawAllocationOrder - Returns the preferred order for allocating /// registers from this register class in MF. The raw order comes directly /// from the .td file and may include reserved registers that are not @@ -276,9 +253,7 @@ public: /// virtual ArrayRef getRawAllocationOrder(const MachineFunction &MF) const { - iterator B = allocation_order_begin(MF); - iterator E = allocation_order_end(MF); - return ArrayRef(B, E - B); + return ArrayRef(begin(), getNumRegs()); } /// getSize - Return the size of the register in bytes, which is also the size diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 6b877826f46..e940b8628d4 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -225,8 +225,6 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) SpillAlignment = R->getValueAsInt("Alignment"); CopyCost = R->getValueAsInt("CopyCost"); Allocatable = R->getValueAsBit("isAllocatable"); - MethodBodies = R->getValueAsCode("MethodBodies"); - MethodProtos = R->getValueAsCode("MethodProtos"); AltOrderSelect = R->getValueAsCode("AltOrderSelect"); } diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index 5e3d5e59c11..5260a144271 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -97,7 +97,7 @@ namespace llvm { bool Allocatable; // Map SubRegIndex -> RegisterClass DenseMap SubRegClasses; - std::string MethodProtos, MethodBodies, AltOrderSelect; + std::string AltOrderSelect; const std::string &getName() const; const std::vector &getValueTypes() const {return VTs;} diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index bcdde342c02..dbde0dbe854 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -117,7 +117,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { if (!RC.AltOrderSelect.empty()) OS << " ArrayRef " "getRawAllocationOrder(const MachineFunction&) const;\n"; - OS << RC.MethodProtos << " };\n"; + OS << " };\n"; // Output the extern for the instance. OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; @@ -356,7 +356,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Emit methods. for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = RegisterClasses[i]; - OS << RC.MethodBodies << "\n"; OS << RC.getName() << "Class::" << RC.getName() << "Class() : TargetRegisterClass(" << RC.getName() + "RegClassID" << ", " -- 2.34.1