From 5080f4d9919d39b367891dc51e739c571a66036c Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 11 Jan 2008 18:10:50 +0000 Subject: [PATCH] rename MachineInstr::setInstrDescriptor -> setDesc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 4 ++-- lib/Target/ARM/ARMConstantIslandPass.cpp | 2 +- lib/Target/ARM/ARMInstrInfo.cpp | 4 ++-- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 +- lib/Target/ARM/ARMRegisterInfo.cpp | 14 +++++++------- lib/Target/Alpha/AlphaBranchSelector.cpp | 2 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +- lib/Target/Sparc/FPMover.cpp | 6 +++--- lib/Target/X86/X86FloatingPoint.cpp | 12 ++++++------ lib/Target/X86/X86InstrInfo.cpp | 8 ++++---- 10 files changed, 28 insertions(+), 28 deletions(-) diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 72463f98d8f..749d1f9a9ae 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -163,10 +163,10 @@ public: /// (before the first implicit operand). void addOperand(const MachineOperand &Op); - /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of + /// setDesc - Replace the instruction descriptor (thus opcode) of /// the current instruction with a new one. /// - void setInstrDescriptor(const TargetInstrDesc &tid) { TID = &tid; } + void setDesc(const TargetInstrDesc &tid) { TID = &tid; } /// RemoveOperand - Erase an operand from an instruction, leaving it with one /// fewer operand than it started with. diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index ea1ee9e39d4..a9f1f5b75f2 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -1162,7 +1162,7 @@ ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &Fn, ImmBranch &Br) { // Use BL to implement far jump. Br.MaxDisp = (1 << 21) * 2; - MI->setInstrDescriptor(TII->get(ARM::tBfar)); + MI->setDesc(TII->get(ARM::tBfar)); BBSizes[MBB->getNumber()] += 2; AdjustBBOffsetsAfter(MBB, 2); HasFarJump = true; diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 52d557e819f..6820e4f5032 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -635,7 +635,7 @@ bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, if (isVarArg) continue; Reg = ARM::PC; - PopMI->setInstrDescriptor(get(ARM::tPOP_RET)); + PopMI->setDesc(get(ARM::tPOP_RET)); MBB.erase(MI); } PopMI->addOperand(MachineOperand::CreateReg(Reg, true)); @@ -792,7 +792,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI, const std::vector &Pred) const { unsigned Opc = MI->getOpcode(); if (Opc == ARM::B || Opc == ARM::tB) { - MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc)); + MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc)); MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); return true; diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 347ed8b3262..6c99c3af341 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -741,7 +741,7 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) { if (PrevMI->getOpcode() == ARM::LDM) { MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1); if (MO.getReg() == ARM::LR) { - PrevMI->setInstrDescriptor(TII->get(ARM::LDM_RET)); + PrevMI->setDesc(TII->get(ARM::LDM_RET)); MO.setReg(ARM::PC); MBB.erase(MBBI); return true; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 01d08414b2b..b3f6d945a36 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -589,14 +589,14 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Offset += MI.getOperand(i+1).getImm(); if (Offset == 0) { // Turn it into a move. - MI.setInstrDescriptor(TII.get(ARM::MOVr)); + MI.setDesc(TII.get(ARM::MOVr)); MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.RemoveOperand(i+1); return; } else if (Offset < 0) { Offset = -Offset; isSub = true; - MI.setInstrDescriptor(TII.get(ARM::SUBri)); + MI.setDesc(TII.get(ARM::SUBri)); } // Common case: small offset, fits into instruction. @@ -629,7 +629,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned Scale = 1; if (FrameReg != ARM::SP) { Opcode = ARM::tADDi3; - MI.setInstrDescriptor(TII.get(ARM::tADDi3)); + MI.setDesc(TII.get(ARM::tADDi3)); NumBits = 3; } else { NumBits = 8; @@ -640,7 +640,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (Offset == 0) { // Turn it into a move. - MI.setInstrDescriptor(TII.get(ARM::tMOVr)); + MI.setDesc(TII.get(ARM::tMOVr)); MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.RemoveOperand(i+1); return; @@ -680,7 +680,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // r0 = -imm (this is then translated into a series of instructons) // r0 = add r0, sp emitThumbConstant(MBB, II, DestReg, Offset, TII, *this); - MI.setInstrDescriptor(TII.get(ARM::tADDhirr)); + MI.setDesc(TII.get(ARM::tADDhirr)); MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); MI.getOperand(i+1).ChangeToRegister(FrameReg, false); } @@ -790,7 +790,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } } else emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this); - MI.setInstrDescriptor(TII.get(ARM::tLDR)); + MI.setDesc(TII.get(ARM::tLDR)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) // Use [reg, reg] addrmode. @@ -827,7 +827,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } } else emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this); - MI.setInstrDescriptor(TII.get(ARM::tSTR)); + MI.setDesc(TII.get(ARM::tSTR)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) // Use [reg, reg] addrmode. MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); diff --git a/lib/Target/Alpha/AlphaBranchSelector.cpp b/lib/Target/Alpha/AlphaBranchSelector.cpp index dba0b9ebf5c..f1d60c836f7 100644 --- a/lib/Target/Alpha/AlphaBranchSelector.cpp +++ b/lib/Target/Alpha/AlphaBranchSelector.cpp @@ -57,7 +57,7 @@ bool AlphaBSel::runOnMachineFunction(MachineFunction &Fn) { // 1. reg // 2. target MBB const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo(); - MBBI->setInstrDescriptor(TII->get(MBBI->getOperand(0).getImm())); + MBBI->setDesc(TII->get(MBBI->getOperand(0).getImm())); } } } diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 19d7afa7f40..b9273af1a48 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -501,7 +501,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, assert(ImmToIdxMap.count(OpC) && "No indexed form of load or store available!"); unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; - MI.setInstrDescriptor(TII.get(NewOpcode)); + MI.setDesc(TII.get(NewOpcode)); OperandBase = 1; } else { OperandBase = OffsetOperandNo; diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index 333cc37178c..016215b9717 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -101,11 +101,11 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { const TargetInstrInfo *TII = TM.getInstrInfo(); if (MI->getOpcode() == SP::FpMOVD) - MI->setInstrDescriptor(TII->get(SP::FMOVS)); + MI->setDesc(TII->get(SP::FMOVS)); else if (MI->getOpcode() == SP::FpNEGD) - MI->setInstrDescriptor(TII->get(SP::FNEGS)); + MI->setDesc(TII->get(SP::FNEGS)); else if (MI->getOpcode() == SP::FpABSD) - MI->setInstrDescriptor(TII->get(SP::FABSS)); + MI->setDesc(TII->get(SP::FABSS)); else assert(0 && "Unknown opcode!"); diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 1b3e0b87495..0310dc8a168 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -535,7 +535,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) { // Check to see if there is a popping version of this instruction... int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode()); if (Opcode != -1) { - I->setInstrDescriptor(TII->get(Opcode)); + I->setDesc(TII->get(Opcode)); if (Opcode == X86::UCOM_FPPr) I->RemoveOperand(0); } else { // Insert an explicit pop @@ -587,7 +587,7 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { // Change from the pseudo instruction to the concrete instruction. MI->RemoveOperand(0); // Remove the explicit ST(0) operand - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); // Result gets pushed on the stack. pushReg(DestReg); @@ -632,7 +632,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { // Convert from the pseudo instruction to the concrete instruction. MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); if (MI->getOpcode() == X86::IST_FP64m || MI->getOpcode() == X86::ISTT_FP16m || @@ -680,7 +680,7 @@ void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { // Change from the pseudo instruction to the concrete instruction. MI->RemoveOperand(1); // Drop the source operand. MI->RemoveOperand(0); // Drop the destination operand. - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); } @@ -878,7 +878,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { // Change from the pseudo instruction to the concrete instruction. MI->getOperand(0).setReg(getSTReg(Op1)); MI->RemoveOperand(1); - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); // If any of the operands are killed by this instruction, free them. if (KillsOp0) freeStackSlotAfter(I, Op0); @@ -904,7 +904,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { MI->RemoveOperand(0); MI->RemoveOperand(1); MI->getOperand(0).setReg(getSTReg(Op1)); - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); // If we kill the second operand, make sure to pop it from the stack. if (Op0 != Op1 && KillsOp1) { diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index bcfd5b2392d..742b18f37cd 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1156,7 +1156,7 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; } - MI->setInstrDescriptor(get(Opc)); + MI->setDesc(get(Opc)); // Fallthrough intended. } default: @@ -1755,7 +1755,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; } // Change to CMPXXri r, 0 first. - MI->setInstrDescriptor(get(NewOpc)); + MI->setDesc(get(NewOpc)); MI->getOperand(1).ChangeToImmediate(0); } else if (Ops.size() != 1) return NULL; @@ -1781,7 +1781,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; } // Change to CMPXXri r, 0 first. - MI->setInstrDescriptor(get(NewOpc)); + MI->setDesc(get(NewOpc)); MI->getOperand(1).ChangeToImmediate(0); } else if (Ops.size() != 1) return NULL; @@ -1936,7 +1936,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, case X86::CMP16ri: NewOpc = X86::TEST16rr; break; case X86::CMP8ri: NewOpc = X86::TEST8rr; break; } - DataMI->setInstrDescriptor(get(NewOpc)); + DataMI->setDesc(get(NewOpc)); MO1.ChangeToRegister(MO0.getReg(), false); } } -- 2.34.1