From 502e0aa62833a1648d66c8f7edf5d21cf96c2f56 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 14 Jul 2010 17:45:16 +0000 Subject: [PATCH] Improve 64-subtraction of immediates when parts of the immediate can fit in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 16 ++++++--- lib/Target/ARM/ARMInstrThumb2.td | 35 +++++++++++++++---- test/CodeGen/ARM/sub.ll | 29 ++++++++++++++++ test/CodeGen/Thumb2/thumb2-sbc.ll | 50 +++++++++++++++++++++++++-- test/CodeGen/Thumb2/thumb2-sub3.ll | 55 ++++++++++++++++++++++++++++++ 5 files changed, 172 insertions(+), 13 deletions(-) create mode 100644 test/CodeGen/ARM/sub.ll create mode 100644 test/CodeGen/Thumb2/thumb2-sub3.ll diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 59a222c8561..51fc1522485 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1694,13 +1694,19 @@ def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), } // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. +// The assume-no-carry-in form uses the negation of the input since add/sub +// assume opposite meanings of the carry flag (i.e., carry == !borrow). +// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory +// details. def : ARMPat<(add GPR:$src, so_imm_neg:$imm), (SUBri GPR:$src, so_imm_neg:$imm)>; - -//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), -// (SUBSri GPR:$src, so_imm_neg:$imm)>; -//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), -// (SBCri GPR:$src, so_imm_neg:$imm)>; +def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), + (SUBSri GPR:$src, so_imm_neg:$imm)>; +// The with-carry-in form matches bitwise not instead of the negation. +// Effectively, the inverse interpretation of the carry flag already accounts +// for part of the negation. +def : ARMPat<(adde GPR:$src, so_imm_not:$imm), + (SBCri GPR:$src, so_imm_not:$imm)>; // Note: These are implemented in C++ code, because they have to generate // ADD/SUBrs instructions, which use a complex pattern that a xform function diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 11413de30dc..bbe675e81ab 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -122,6 +122,10 @@ def imm0_255_neg : PatLeaf<(i32 imm), [{ return (uint32_t)(-N->getZExtValue()) < 255; }], imm_neg_XFORM>; +def imm0_255_not : PatLeaf<(i32 imm), [{ + return (uint32_t)(~N->getZExtValue()) < 255; +}], imm_comp_XFORM>; + // Define Thumb2 specific addressing modes. // t2addrmode_imm12 := reg + imm12 @@ -1391,13 +1395,32 @@ defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. +// The assume-no-carry-in form uses the negation of the input since add/sub +// assume opposite meanings of the carry flag (i.e., carry == !borrow). +// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory +// details. +// The AddedComplexity preferences the first variant over the others since +// it can be shrunk to a 16-bit wide encoding, while the others cannot. +let AddedComplexity = 1 in +def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), + (t2SUBri GPR:$src, imm0_255_neg:$imm)>; +def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), + (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; +def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), + (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; +let AddedComplexity = 1 in +def : T2Pat<(addc GPR:$src, imm0_255_neg:$imm), + (t2SUBSri GPR:$src, imm0_255_neg:$imm)>; +def : T2Pat<(addc GPR:$src, t2_so_imm_neg:$imm), + (t2SUBSri GPR:$src, t2_so_imm_neg:$imm)>; +// The with-carry-in form matches bitwise not instead of the negation. +// Effectively, the inverse interpretation of the carry flag already accounts +// for part of the negation. let AddedComplexity = 1 in -def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), - (t2SUBri GPR:$src, imm0_255_neg:$imm)>; -def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), - (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; -def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), - (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; +def : T2Pat<(adde GPR:$src, imm0_255_not:$imm), + (t2SBCSri GPR:$src, imm0_255_not:$imm)>; +def : T2Pat<(adde GPR:$src, t2_so_imm_not:$imm), + (t2SBCSri GPR:$src, t2_so_imm_not:$imm)>; // Select Bytes -- for disassembly only diff --git a/test/CodeGen/ARM/sub.ll b/test/CodeGen/ARM/sub.ll new file mode 100644 index 00000000000..81513e23e80 --- /dev/null +++ b/test/CodeGen/ARM/sub.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=arm < %s | FileCheck %s + +; 171 = 0x000000ab +define i64 @f1(i64 %a) { +; CHECK: f1 +; CHECK: subs r0, r0, #171 +; CHECK: sbc r1, r1, #0 + %tmp = sub i64 %a, 171 + ret i64 %tmp +} + +; 66846720 = 0x03fc0000 +define i64 @f2(i64 %a) { +; CHECK: f2 +; CHECK: subs r0, r0, #255, 14 +; CHECK: sbc r1, r1, #0 + %tmp = sub i64 %a, 66846720 + ret i64 %tmp +} + +; 734439407618 = 0x000000ab00000002 +define i64 @f3(i64 %a) { +; CHECK: f3 +; CHECK: subs r0, r0, #2 +; CHECK: sbc r1, r1, #171 + %tmp = sub i64 %a, 734439407618 + ret i64 %tmp +} + diff --git a/test/CodeGen/Thumb2/thumb2-sbc.ll b/test/CodeGen/Thumb2/thumb2-sbc.ll index ad962919edc..de6502d2e63 100644 --- a/test/CodeGen/Thumb2/thumb2-sbc.ll +++ b/test/CodeGen/Thumb2/thumb2-sbc.ll @@ -1,8 +1,54 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc -march=thumb -mattr=+thumb2 < %s | FileCheck %s define i64 @f1(i64 %a, i64 %b) { -; CHECK: f1: +; CHECK: f1 ; CHECK: subs r0, r0, r2 %tmp = sub i64 %a, %b ret i64 %tmp } + +; 734439407618 = 0x000000ab00000002 +define i64 @f2(i64 %a) { +; CHECK: f2 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #171 + %tmp = sub i64 %a, 734439407618 + ret i64 %tmp +} + +; 5066626890203138 = 0x0012001200000002 +define i64 @f3(i64 %a) { +; CHECK: f3 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #1179666 + %tmp = sub i64 %a, 5066626890203138 + ret i64 %tmp +} + +; 3747052064576897026 = 0x3400340000000002 +define i64 @f4(i64 %a) { +; CHECK: f4 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #872428544 + %tmp = sub i64 %a, 3747052064576897026 + ret i64 %tmp +} + +; 6221254862626095106 = 0x5656565600000002 +define i64 @f5(i64 %a) { +; CHECK: f5 +; CHECK: subs r0, #2 +; CHECK: adc r1, r1, #-1448498775 + %tmp = sub i64 %a, 6221254862626095106 + ret i64 %tmp +} + +; 287104476244869122 = 0x03fc000000000002 +define i64 @f6(i64 %a) { +; CHECK: f6 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #66846720 + %tmp = sub i64 %a, 287104476244869122 + ret i64 %tmp +} + diff --git a/test/CodeGen/Thumb2/thumb2-sub3.ll b/test/CodeGen/Thumb2/thumb2-sub3.ll new file mode 100644 index 00000000000..855ad06a63f --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-sub3.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=thumb -mattr=+thumb2 < %s | FileCheck %s + +; 171 = 0x000000ab +define i64 @f1(i64 %a) { +; CHECK: f1 +; CHECK: subs r0, #171 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 171 + ret i64 %tmp +} + +; 1179666 = 0x00120012 +define i64 @f2(i64 %a) { +; CHECK: f2 +; CHECK: subs.w r0, r0, #1179666 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 1179666 + ret i64 %tmp +} + +; 872428544 = 0x34003400 +define i64 @f3(i64 %a) { +; CHECK: f3 +; CHECK: subs.w r0, r0, #872428544 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 872428544 + ret i64 %tmp +} + +; 1448498774 = 0x56565656 +define i64 @f4(i64 %a) { +; CHECK: f4 +; CHECK: subs.w r0, r0, #1448498774 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 1448498774 + ret i64 %tmp +} + +; 66846720 = 0x03fc0000 +define i64 @f5(i64 %a) { +; CHECK: f5 +; CHECK: subs.w r0, r0, #66846720 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 66846720 + ret i64 %tmp +} + +; 734439407618 = 0x000000ab00000002 +define i64 @f6(i64 %a) { +; CHECK: f6 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #171 + %tmp = sub i64 %a, 734439407618 + ret i64 %tmp +} -- 2.34.1